This is a short summary of the A\+V\+R-\/specific aspects of using the G\+NU tools. Normally, the generic documentation of these tools is fairly large and maintained in {\ttfamily texinfo} files. Command-\/line options are explained in detail in the manual page.\hypertarget{using_tools_using_avr_gcc}{}\doxysubsection{Options for the C compiler avr-\/gcc}\label{using_tools_using_avr_gcc}
\hypertarget{using_tools_using_avr_gcc_mach_opt}{}\doxysubsubsection{Machine-\/specific options for the A\+VR}\label{using_tools_using_avr_gcc_mach_opt}
The following machine-\/specific options are recognized by the C compiler frontend. In addition to the preprocessor macros indicated in the tables below, the preprocessor will define the macros \+\_\+\+\_\+\+A\+VR and \+\_\+\+\_\+\+A\+V\+R\+\_\+\+\_\+ (to the value 1) when compiling for an A\+VR target. The macro A\+VR will be defined as well when using the standard levels gnu89 (default) and gnu99 but not with c89 and c99.


\begin{DoxyItemize}
\item {\ttfamily -\/mmcu=}{\itshape architecture} 
\end{DoxyItemize}

Compile code for {\itshape architecture}. Currently known architectures are 

\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{3}{|X[-1]}|}
\hline
Architecture &Macros &Description  \\\cline{1-3}
avr1 &\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+R\+C\+H\+\_\+\+\_\+=1~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+S\+M\+\_\+\+O\+N\+L\+Y\+\_\+\+\_\+~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+2\+\_\+\+B\+Y\+T\+E\+\_\+\+P\+C\+\_\+\+\_\+~\mbox{[}2\mbox{]}  &Simple C\+PU core, only assembler support  \\\cline{1-3}
avr2 &\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+R\+C\+H\+\_\+\+\_\+=2~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+2\+\_\+\+B\+Y\+T\+E\+\_\+\+P\+C\+\_\+\+\_\+~\mbox{[}2\mbox{]}  &\char`\"{}\+Classic\char`\"{} C\+PU core, up to 8 KB of R\+OM  \\\cline{1-3}
avr25~\mbox{[}1\mbox{]} &\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+R\+C\+H\+\_\+\+\_\+=25~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+M\+O\+V\+W\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+L\+P\+M\+X\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+2\+\_\+\+B\+Y\+T\+E\+\_\+\+P\+C\+\_\+\+\_\+~\mbox{[}2\mbox{]}  &\char`\"{}\+Classic\char`\"{} C\+PU core with \textquotesingle{}M\+O\+VW\textquotesingle{} and \textquotesingle{}L\+PM Rx, Z\mbox{[}+\mbox{]}\textquotesingle{} instruction, up to 8 KB of R\+OM  \\\cline{1-3}
avr3 &\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+R\+C\+H\+\_\+\+\_\+=3~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+M\+E\+G\+A\+\_\+\+\_\+~\mbox{[}5\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+J\+M\+P\+\_\+\+C\+A\+L\+L\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+2\+\_\+\+B\+Y\+T\+E\+\_\+\+P\+C\+\_\+\+\_\+~\mbox{[}2\mbox{]}  &\char`\"{}\+Classic\char`\"{} C\+PU core, 16 KB to 64 KB of R\+OM  \\\cline{1-3}
avr31 &\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+R\+C\+H\+\_\+\+\_\+=31~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+M\+E\+G\+A\+\_\+\+\_\+~\mbox{[}5\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+J\+M\+P\+\_\+\+C\+A\+L\+L\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+R\+A\+M\+P\+Z\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+E\+L\+P\+M\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+2\+\_\+\+B\+Y\+T\+E\+\_\+\+P\+C\+\_\+\+\_\+~\mbox{[}2\mbox{]}  &\char`\"{}\+Classic\char`\"{} C\+PU core, 128 KB of R\+OM  \\\cline{1-3}
avr35~\mbox{[}3\mbox{]} &\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+R\+C\+H\+\_\+\+\_\+=35~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+M\+E\+G\+A\+\_\+\+\_\+~\mbox{[}5\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+J\+M\+P\+\_\+\+C\+A\+L\+L\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+M\+O\+V\+W\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+L\+P\+M\+X\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+2\+\_\+\+B\+Y\+T\+E\+\_\+\+P\+C\+\_\+\+\_\+~\mbox{[}2\mbox{]}  &\char`\"{}\+Classic\char`\"{} C\+PU core with \textquotesingle{}M\+O\+VW\textquotesingle{} and \textquotesingle{}L\+PM Rx, Z\mbox{[}+\mbox{]}\textquotesingle{} instruction, 16 KB to 64 KB of R\+OM  \\\cline{1-3}
avr4 &\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+R\+C\+H\+\_\+\+\_\+=4~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+E\+N\+H\+A\+N\+C\+E\+D\+\_\+\+\_\+~\mbox{[}5\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+M\+O\+V\+W\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+L\+P\+M\+X\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+M\+U\+L\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+2\+\_\+\+B\+Y\+T\+E\+\_\+\+P\+C\+\_\+\+\_\+~\mbox{[}2\mbox{]}  &\char`\"{}\+Enhanced\char`\"{} C\+PU core, up to 8 KB of R\+OM  \\\cline{1-3}
avr5 &\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+R\+C\+H\+\_\+\+\_\+=5~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+M\+E\+G\+A\+\_\+\+\_\+~\mbox{[}5\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+E\+N\+H\+A\+N\+C\+E\+D\+\_\+\+\_\+~\mbox{[}5\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+J\+M\+P\+\_\+\+C\+A\+L\+L\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+M\+O\+V\+W\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+L\+P\+M\+X\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+M\+U\+L\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+2\+\_\+\+B\+Y\+T\+E\+\_\+\+P\+C\+\_\+\+\_\+~\mbox{[}2\mbox{]}  &\char`\"{}\+Enhanced\char`\"{} C\+PU core, 16 KB to 64 KB of R\+OM  \\\cline{1-3}
avr51 &\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+R\+C\+H\+\_\+\+\_\+=51~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+M\+E\+G\+A\+\_\+\+\_\+~\mbox{[}5\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+E\+N\+H\+A\+N\+C\+E\+D\+\_\+\+\_\+~\mbox{[}5\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+J\+M\+P\+\_\+\+C\+A\+L\+L\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+M\+O\+V\+W\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+L\+P\+M\+X\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+M\+U\+L\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+R\+A\+M\+P\+Z\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+E\+L\+P\+M\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+E\+L\+P\+M\+X\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+2\+\_\+\+B\+Y\+T\+E\+\_\+\+P\+C\+\_\+\+\_\+~\mbox{[}2\mbox{]}  &\char`\"{}\+Enhanced\char`\"{} C\+PU core, 128 KB of R\+OM  \\\cline{1-3}
avr6~\mbox{[}2\mbox{]} &\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+R\+C\+H\+\_\+\+\_\+=6~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+M\+E\+G\+A\+\_\+\+\_\+~\mbox{[}5\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+E\+N\+H\+A\+N\+C\+E\+D\+\_\+\+\_\+~\mbox{[}5\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+J\+M\+P\+\_\+\+C\+A\+L\+L\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+M\+O\+V\+W\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+L\+P\+M\+X\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+M\+U\+L\+\_\+\+\_\+~\mbox{[}1\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+R\+A\+M\+P\+Z\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+E\+L\+P\+M\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+\+H\+A\+V\+E\+\_\+\+E\+L\+P\+M\+X\+\_\+\+\_\+~\mbox{[}4\mbox{]}~\newline
 \+\_\+\+\_\+\+A\+V\+R\+\_\+3\+\_\+\+B\+Y\+T\+E\+\_\+\+P\+C\+\_\+\+\_\+~\mbox{[}2\mbox{]}  &\char`\"{}\+Enhanced\char`\"{} C\+PU core, 256 KB of R\+OM  \\\cline{1-3}
\end{longtabu}


\mbox{[}1\mbox{]} New in G\+CC 4.\+2~\newline
 \mbox{[}2\mbox{]} Unofficial patch for G\+CC 4.\+1~\newline
 \mbox{[}3\mbox{]} New in G\+CC 4.\+2.\+3~\newline
 \mbox{[}4\mbox{]} New in G\+CC 4.\+3~\newline
 \mbox{[}5\mbox{]} Obsolete. 

By default, code is generated for the avr2 architecture. 

Note that when only using {\ttfamily -\/mmcu=}{\itshape architecture} but no {\ttfamily -\/mmcu=}{\itshape M\+CU type}, including the file {\ttfamily $<$\mbox{\hyperlink{io_8h}{avr/io.\+h}}$>$} cannot work since it cannot decide which device\textquotesingle{}s definitions to select. 


\begin{DoxyItemize}
\item {\ttfamily -\/mmcu=}{\itshape M\+CU type} 
\end{DoxyItemize}

The following M\+CU types are currently understood by avr-\/gcc. The table matches them against the corresponding avr-\/gcc architecture name, and shows the preprocessor symbol declared by the {\ttfamily -\/mmcu} option. 

\tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{3}{|X[-1]}|}
\hline
Architecture&M\+CU name&Macro

\\\cline{1-3}
avr1&at90s1200&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+S1200\+\_\+\+\_\+ \\\cline{1-3}
avr1&attiny11&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny11\+\_\+\+\_\+ \\\cline{1-3}
avr1&attiny12&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny12\+\_\+\+\_\+ \\\cline{1-3}
avr1&attiny15&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny15\+\_\+\+\_\+ \\\cline{1-3}
avr1&attiny28&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny28\+\_\+\+\_\+

\\\cline{1-3}
avr2&at90s2313&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+S2313\+\_\+\+\_\+ \\\cline{1-3}
avr2&at90s2323&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+S2323\+\_\+\+\_\+ \\\cline{1-3}
avr2&at90s2333&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+S2333\+\_\+\+\_\+ \\\cline{1-3}
avr2&at90s2343&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+S2343\+\_\+\+\_\+ \\\cline{1-3}
avr2&attiny22&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny22\+\_\+\+\_\+ \\\cline{1-3}
avr2&attiny26&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny26\+\_\+\+\_\+ \\\cline{1-3}
avr2&at90s4414&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+S4414\+\_\+\+\_\+ \\\cline{1-3}
avr2&at90s4433&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+S4433\+\_\+\+\_\+ \\\cline{1-3}
avr2&at90s4434&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+S4434\+\_\+\+\_\+ \\\cline{1-3}
avr2&at90s8515&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+S8515\+\_\+\+\_\+ \\\cline{1-3}
avr2&at90c8534&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+C8534\+\_\+\+\_\+ \\\cline{1-3}
avr2&at90s8535&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+S8535\+\_\+\+\_\+

\\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&at86rf401&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T86\+R\+F401\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&ata5272&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T\+A5272\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&ata6616c&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T\+A6616\+C\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny13&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny13\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny13a&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny13\+A\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny2313&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny2313\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny2313a&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny2313\+A\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny24&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny24\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny24a&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny24\+A\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny25&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny25\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny261&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny261\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny261a&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny261\+A\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny4313&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny4313\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny43u&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny43\+U\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny44&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny44\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny44a&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny44\+A\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny441&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny441\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny45&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny45\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny461&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny461\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny461a&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny461\+A\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny48&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny48\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny828&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny828\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny84&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny84\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny84a&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny84\+A\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny841&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny841\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny85&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny85\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny861&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny861\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny861a&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny861\+A\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny87&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny87\+\_\+\+\_\+ \\\cline{1-3}
avr2/avr25~\mbox{[}1\mbox{]}&attiny88&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny88\+\_\+\+\_\+

\\\cline{1-3}
avr3&atmega603&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Tmega603\+\_\+\+\_\+ \\\cline{1-3}
avr3&at43usb355&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T43\+U\+S\+B355\+\_\+\+\_\+

\\\cline{1-3}
avr3/avr31~\mbox{[}3\mbox{]}&atmega103&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Tmega103\+\_\+\+\_\+ \\\cline{1-3}
avr3/avr31~\mbox{[}3\mbox{]}&at43usb320&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T43\+U\+S\+B320\+\_\+\+\_\+

\\\cline{1-3}
avr3/avr35~\mbox{[}2\mbox{]}&at90usb82&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+U\+S\+B82\+\_\+\+\_\+ \\\cline{1-3}
avr3/avr35~\mbox{[}2\mbox{]}&at90usb162&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T90\+U\+S\+B162\+\_\+\+\_\+ \\\cline{1-3}
avr3/avr35~\mbox{[}2\mbox{]}&ata5505&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T\+A5505\+\_\+\+\_\+ \\\cline{1-3}
avr3/avr35~\mbox{[}2\mbox{]}&ata6617c&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T\+A6617\+C\+\_\+\+\_\+ \\\cline{1-3}
avr3/avr35~\mbox{[}2\mbox{]}&ata664251&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+T\+A664251\+\_\+\+\_\+ \\\cline{1-3}
avr3/avr35~\mbox{[}2\mbox{]}&atmega8u2&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Tmega8\+U2\+\_\+\+\_\+ \\\cline{1-3}
avr3/avr35~\mbox{[}2\mbox{]}&atmega16u2&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Tmega16\+U2\+\_\+\+\_\+ \\\cline{1-3}
avr3/avr35~\mbox{[}2\mbox{]}&atmega32u2&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Tmega32\+U2\+\_\+\+\_\+ \\\cline{1-3}
avr3/avr35~\mbox{[}2\mbox{]}&attiny167&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny167\+\_\+\+\_\+ \\\cline{1-3}
avr3/avr35~\mbox{[}2\mbox{]}&attiny1634&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny1634\+\_\+\+\_\+

\\\cline{1-3}
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avrxmega4&atxmega64a3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega64\+A3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega4&atxmega64a3u&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega64\+A3\+U\+\_\+\+\_\+ \\\cline{1-3}
avrxmega4&atxmega64a4u&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega64\+A4\+U\+\_\+\+\_\+ \\\cline{1-3}
avrxmega4&atxmega64b1&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega64\+B1\+\_\+\+\_\+ \\\cline{1-3}
avrxmega4&atxmega64b3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega64\+B3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega4&atxmega64c3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega64\+C3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega4&atxmega64d3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega64\+D3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega4&atxmega64d4&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega64\+D4\+\_\+\+\_\+

\\\cline{1-3}
avrxmega5&atxmega64a1&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega64\+A1\+\_\+\+\_\+ \\\cline{1-3}
avrxmega5&atxmega64a1u&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega64\+A1\+U\+\_\+\+\_\+

\\\cline{1-3}
avrxmega6&atxmega128a3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega128\+A3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega128a3u&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega128\+A3\+U\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega128b1&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega128\+B1\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega128b3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega128\+B3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega128c3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega128\+C3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega128d3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega128\+D3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega128d4&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega128\+D4\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega192a3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega192\+A3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega192a3u&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega192\+A3\+U\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega192c3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega192\+C3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega192d3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega192\+D3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega256a3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega256\+A3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega256a3u&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega256\+A3\+U\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega256a3b&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega256\+A3\+B\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega256a3bu&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega256\+A3\+B\+U\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega256c3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega256\+C3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega256d3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega256\+D3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega384c3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega384\+C3\+\_\+\+\_\+ \\\cline{1-3}
avrxmega6&atxmega384d3&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega384\+D3\+\_\+\+\_\+

\\\cline{1-3}
avrxmega7&atxmega128a1&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega128\+A1\+\_\+\+\_\+ \\\cline{1-3}
avrxmega7&atxmega128a1u&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega128\+A1\+U\+\_\+\+\_\+ \\\cline{1-3}
avrxmega7&atxmega128a4u&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Txmega128\+A4\+U\+\_\+\+\_\+

\\\cline{1-3}
avrtiny10&attiny4&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny4\+\_\+\+\_\+ \\\cline{1-3}
avrtiny10&attiny5&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny5\+\_\+\+\_\+ \\\cline{1-3}
avrtiny10&attiny9&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny9\+\_\+\+\_\+ \\\cline{1-3}
avrtiny10&attiny10&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny10\+\_\+\+\_\+ \\\cline{1-3}
avrtiny10&attiny20&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny20\+\_\+\+\_\+ \\\cline{1-3}
avrtiny10&attiny40&\+\_\+\+\_\+\+A\+V\+R\+\_\+\+A\+Ttiny40\+\_\+\+\_\+

\\\cline{1-3}
\end{longtabu}


\mbox{[}1\mbox{]} \textquotesingle{}avr25\textquotesingle{} architecture is new in G\+CC 4.\+2~\newline
 \mbox{[}2\mbox{]} \textquotesingle{}avr35\textquotesingle{} architecture is new in G\+CC 4.\+2.\+3~\newline
 \mbox{[}3\mbox{]} \textquotesingle{}avr31\textquotesingle{} and \textquotesingle{}avr51\textquotesingle{} architectures is new in G\+CC 4.\+3 


\begin{DoxyItemize}
\item {\ttfamily -\/morder1} 
\item {\ttfamily -\/morder2} 
\end{DoxyItemize}

Change the order of register assignment. The default is 

r24, r25, r18, r19, r20, r21, r22, r23, r30, r31, r26, r27, r28, r29, r17, r16, r15, r14, r13, r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r0, r1 

Order 1 uses 

r18, r19, r20, r21, r22, r23, r24, r25, r30, r31, r26, r27, r28, r29, r17, r16, r15, r14, r13, r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r0, r1 

Order 2 uses 

r25, r24, r23, r22, r21, r20, r19, r18, r30, r31, r26, r27, r28, r29, r17, r16, r15, r14, r13, r12, r11, r10, r9, r8, r7, r6, r5, r4, r3, r2, r1, r0 


\begin{DoxyItemize}
\item {\ttfamily -\/mint8} 
\end{DoxyItemize}

Assume {\ttfamily int} to be an 8-\/bit integer. Note that this is not really supported by {\ttfamily avr-\/libc}, so it should normally not be used. The default is to use 16-\/bit integers. 


\begin{DoxyItemize}
\item {\ttfamily -\/mno-\/interrupts} 
\end{DoxyItemize}

Generates code that changes the stack pointer without disabling interrupts. Normally, the state of the status register {\ttfamily S\+R\+EG} is saved in a temporary register, interrupts are disabled while changing the stack pointer, and {\ttfamily S\+R\+EG} is restored. 

Specifying this option will define the preprocessor macro {\ttfamily \+\_\+\+\_\+\+N\+O\+\_\+\+I\+N\+T\+E\+R\+R\+U\+P\+T\+S\+\_\+\+\_\+} to the value 1. 


\begin{DoxyItemize}
\item {\ttfamily -\/mcall-\/prologues} 
\end{DoxyItemize}

Use subroutines for function prologue/epilogue. For complex functions that use many registers (that needs to be saved/restored on function entry/exit), this saves some space at the cost of a slightly increased execution time. 


\begin{DoxyItemize}
\item {\ttfamily -\/mtiny-\/stack} 
\end{DoxyItemize}

Change only the low 8 bits of the stack pointer. 


\begin{DoxyItemize}
\item {\ttfamily -\/mno-\/tablejump} 
\end{DoxyItemize}

Deprecated, use {\ttfamily -\/fno-\/jump-\/tables} instead. 


\begin{DoxyItemize}
\item {\ttfamily -\/mshort-\/calls} 
\end{DoxyItemize}

Use {\ttfamily rjmp/rcall} (limited range) on $>$8K devices. On {\ttfamily avr2} and {\ttfamily avr4} architectures (less than 8 KB or flash memory), this is always the case. On {\ttfamily avr3} and {\ttfamily avr5} architectures, calls and jumps to targets outside the current function will by default use {\ttfamily jmp/call} instructions that can cover the entire address range, but that require more flash R\+OM and execution time. 


\begin{DoxyItemize}
\item {\ttfamily -\/mrtl} 
\end{DoxyItemize}

Dump the internal compilation result called \char`\"{}\+R\+T\+L\char`\"{} into comments in the generated assembler code. Used for debugging avr-\/gcc. 


\begin{DoxyItemize}
\item {\ttfamily -\/msize} 
\end{DoxyItemize}

Dump the address, size, and relative cost of each statement into comments in the generated assembler code. Used for debugging avr-\/gcc. 


\begin{DoxyItemize}
\item {\ttfamily -\/mdeb} 
\end{DoxyItemize}

Generate lots of debugging information to {\ttfamily stderr}. \hypertarget{using_tools_using_sel_gcc_opts}{}\doxysubsubsection{Selected general compiler options}\label{using_tools_using_sel_gcc_opts}
The following general gcc options might be of some interest to A\+VR users.


\begin{DoxyItemize}
\item {\ttfamily -\/O}{\itshape n} 
\end{DoxyItemize}

\label{using_tools_gcc_optO}%
\Hypertarget{using_tools_gcc_optO}%
 Optimization level {\itshape n}. Increasing {\itshape n} is meant to optimize more, an optimization level of 0 means no optimization at all, which is the default if no {\ttfamily -\/O} option is present. The special option {\ttfamily -\/Os} is meant to turn on all {\ttfamily -\/O2} optimizations that are not expected to increase code size. 

Note that at {\ttfamily -\/O3}, gcc attempts to inline all \char`\"{}simple\char`\"{} functions. For the A\+VR target, this will normally constitute a large pessimization due to the code increasement. The only other optimization turned on with {\ttfamily -\/O3} is {\ttfamily -\/frename-\/registers}, which could rather be enabled manually instead. 

A simple {\ttfamily -\/O} option is equivalent to {\ttfamily -\/O1}. 

Note also that turning off all optimizations will prevent some warnings from being issued since the generation of those warnings depends on code analysis steps that are only performed when optimizing (unreachable code, unused variables). 

See also the \mbox{\hyperlink{FAQ_faq_gdboptimize}{appropriate F\+AQ entry}} for issues regarding debugging optimized code. 


\begin{DoxyItemize}
\item {\ttfamily -\/Wa,}{\itshape assembler-\/options}
\item {\ttfamily -\/Wl,}{\itshape linker-\/options} 
\end{DoxyItemize}

\label{using_tools_gcc_minusW}%
\Hypertarget{using_tools_gcc_minusW}%
 Pass the listed options to the assembler, or linker, respectively. 


\begin{DoxyItemize}
\item {\ttfamily -\/g} 
\end{DoxyItemize}

Generate debugging information that can be used by avr-\/gdb. 


\begin{DoxyItemize}
\item {\ttfamily -\/ffreestanding} 
\end{DoxyItemize}

Assume a \char`\"{}freestanding\char`\"{} environment as per the C standard. This turns off automatic builtin functions (though they can still be reached by prepending {\ttfamily \+\_\+\+\_\+builtin\+\_\+} to the actual function name). It also makes the compiler not complain when {\ttfamily main()} is declared with a {\ttfamily void} return type which makes some sense in a microcontroller environment where the application cannot meaningfully provide a return value to its environment (in most cases, {\ttfamily main()} won\textquotesingle{}t even return anyway). However, this also turns off all optimizations normally done by the compiler which assume that functions known by a certain name behave as described by the standard. E. g., applying the function strlen() to a literal string will normally cause the compiler to immediately replace that call by the actual length of the string, while with {\ttfamily -\/ffreestanding}, it will always call strlen() at run-\/time. 


\begin{DoxyItemize}
\item {\ttfamily -\/funsigned-\/char} 
\end{DoxyItemize}

Make any unqualfied {\ttfamily char} type an unsigned char. Without this option, they default to a signed char. 


\begin{DoxyItemize}
\item {\ttfamily -\/funsigned-\/bitfields} 
\end{DoxyItemize}

Make any unqualified bitfield type unsigned. By default, they are signed. 


\begin{DoxyItemize}
\item {\ttfamily -\/fshort-\/enums} 
\end{DoxyItemize}

Allocate to an {\ttfamily enum} type only as many bytes as it needs for the declared range of possible values. Specifically, the enum type will be equivalent to the smallest integer type which has enough room. 


\begin{DoxyItemize}
\item {\ttfamily -\/fpack-\/struct} 
\end{DoxyItemize}

Pack all structure members together without holes. 


\begin{DoxyItemize}
\item {\ttfamily -\/fno-\/jump-\/tables} 
\end{DoxyItemize}

Do not generate tablejump instructions. By default, jump tables can be used to optimize {\ttfamily switch} statements. When turned off, sequences of compare statements are used instead. Jump tables are usually faster to execute on average, but in particular for {\ttfamily switch} statements, where most of the jumps would go to the default label, they might waste a bit of flash memory. 

N\+O\+TE\+: The tablejump instructions use the L\+PM assembler instruction for access to jump tables. Always use {\ttfamily -\/fno-\/jump-\/tables} switch, if compiling a bootloader for devices with more than 64 KB of code memory. \hypertarget{using_tools_using_avr_as}{}\doxysubsection{Options for the assembler avr-\/as}\label{using_tools_using_avr_as}
\hypertarget{using_tools_using_avr_as_mach_opts}{}\doxysubsubsection{Machine-\/specific assembler options}\label{using_tools_using_avr_as_mach_opts}

\begin{DoxyItemize}
\item {\ttfamily -\/mmcu=}{\itshape architecture}
\item {\ttfamily -\/mmcu=}{\itshape M\+CU name} 
\end{DoxyItemize}

avr-\/as understands the same {\ttfamily -\/mmcu=} options as \mbox{\hyperlink{using_tools_using_avr_gcc}{avr-\/gcc}}. By default, avr2 is assumed, but this can be altered by using the appropriate {\ttfamily }.arch pseudo-\/instruction inside the assembler source file. 


\begin{DoxyItemize}
\item {\ttfamily -\/mall-\/opcodes} 
\end{DoxyItemize}

Turns off opcode checking for the actual M\+CU type, and allows any possible A\+VR opcode to be assembled. 


\begin{DoxyItemize}
\item {\ttfamily -\/mno-\/skip-\/bug} 
\end{DoxyItemize}

Don\textquotesingle{}t emit a warning when trying to skip a 2-\/word instruction with a {\ttfamily C\+P\+S\+E/\+S\+B\+I\+C/\+S\+B\+I\+S/\+S\+B\+R\+C/\+S\+B\+RS} instruction. Early A\+VR devices suffered from a hardware bug where these instructions could not be properly skipped. 


\begin{DoxyItemize}
\item {\ttfamily -\/mno-\/wrap} 
\end{DoxyItemize}

For {\ttfamily R\+J\+M\+P/\+R\+C\+A\+LL} instructions, don\textquotesingle{}t allow the target address to wrap around for devices that have more than 8 KB of memory. 


\begin{DoxyItemize}
\item {\ttfamily --gstabs} 
\end{DoxyItemize}

Generate {\ttfamily }.stabs debugging symbols for assembler source lines. This enables avr-\/gdb to trace through assembler source files. This option {\itshape must not} be used when assembling sources that have been generated by the C compiler; these files already contain the appropriate line number information from the C source files. 


\begin{DoxyItemize}
\item {\ttfamily -\/a\mbox{[}cdhlmns=}{\itshape file}{\ttfamily \mbox{]}} 
\end{DoxyItemize}

Turn on the assembler listing. The sub-\/options are\+: 


\begin{DoxyItemize}
\item {\ttfamily c} omit false conditionals 
\item {\ttfamily d} omit debugging directives 
\item {\ttfamily h} include high-\/level source 
\item {\ttfamily l} include assembly 
\item {\ttfamily m} include macro expansions 
\item {\ttfamily n} omit forms processing 
\item {\ttfamily s} include symbols 
\item {\ttfamily =}{\itshape file} set the name of the listing file 
\end{DoxyItemize}

The various sub-\/options can be combined into a single {\ttfamily -\/a} option list; {\itshape =file} must be the last one in that case. \hypertarget{using_tools_using_avr_example}{}\doxysubsubsection{Examples for assembler options passed through the C compiler}\label{using_tools_using_avr_example}
Remember that assembler options can be passed from the C compiler frontend using {\ttfamily -\/Wa} (see \mbox{\hyperlink{using_tools_gcc_minusW}{above}}), so in order to include the C source code into the assembler listing in file {\ttfamily foo.\+lst}, when compiling {\ttfamily foo.\+c}, the following compiler command-\/line can be used\+:

\begin{DoxyVerb}	$ avr-gcc -c -O foo.c -o foo.o -Wa,-ahls=foo.lst
\end{DoxyVerb}


In order to pass an assembler file through the C preprocessor first, and have the assembler generate line number debugging information for it, the following command can be used\+:

\begin{DoxyVerb}	$ avr-gcc -c -x assembler-with-cpp -o foo.o foo.S -Wa,--gstabs
\end{DoxyVerb}


Note that on Unix systems that have case-\/distinguishing file systems, specifying a file name with the suffix {\ttfamily }.S (upper-\/case letter S) will make the compiler automatically assume {\ttfamily -\/x assembler-\/with-\/cpp}, while using {\ttfamily }.s would pass the file directly to the assembler (no preprocessing done).\hypertarget{using_tools_using_avr_ld}{}\doxysubsection{Controlling the linker avr-\/ld}\label{using_tools_using_avr_ld}
\hypertarget{using_tools_using_sel_ld_opts}{}\doxysubsubsection{Selected linker options}\label{using_tools_using_sel_ld_opts}
While there are no machine-\/specific options for avr-\/ld, a number of the standard options might be of interest to A\+VR users.


\begin{DoxyItemize}
\item {\ttfamily -\/l}{\itshape name} 
\end{DoxyItemize}

Locate the archive library named {\ttfamily lib}{\itshape name}{\ttfamily .a}, and use it to resolve currently unresolved symbols from it. The library is searched along a path that consists of builtin pathname entries that have been specified at compile time (e. g. {\ttfamily /usr/local/avr/lib} on Unix systems), possibly extended by pathname entries as specified by {\ttfamily -\/L} options (that must precede the {\ttfamily -\/l} options on the command-\/line). 


\begin{DoxyItemize}
\item {\ttfamily -\/L}{\itshape path} 
\end{DoxyItemize}

Additional location to look for archive libraries requested by {\ttfamily -\/l} options. 


\begin{DoxyItemize}
\item {\ttfamily --defsym }{\itshape symbol=expr} 
\end{DoxyItemize}

Define a global symbol {\itshape symbol} using {\itshape expr} as the value. 


\begin{DoxyItemize}
\item {\ttfamily -\/M} 
\end{DoxyItemize}

Print a linker map to {\ttfamily stdout}. 


\begin{DoxyItemize}
\item {\ttfamily -\/Map }{\itshape mapfile} 
\end{DoxyItemize}

Print a linker map to {\itshape mapfile}. 


\begin{DoxyItemize}
\item {\ttfamily --cref} 
\end{DoxyItemize}

Output a cross reference table to the map file (in case {\ttfamily -\/Map} is also present), or to {\ttfamily stdout}. 


\begin{DoxyItemize}
\item {\ttfamily --section-\/start }{\itshape sectionname=org} 
\end{DoxyItemize}

Start section {\itshape sectionname} at absolute address {\itshape org}. 


\begin{DoxyItemize}
\item {\ttfamily -\/Tbss }{\itshape org}
\item {\ttfamily -\/Tdata }{\itshape org}
\item {\ttfamily -\/Ttext }{\itshape org} 
\end{DoxyItemize}

Start the {\ttfamily bss}, {\ttfamily data}, or {\ttfamily text} section at {\itshape org}, respectively. 


\begin{DoxyItemize}
\item {\ttfamily -\/T }{\itshape scriptfile} 
\end{DoxyItemize}

Use {\itshape scriptfile} as the linker script, replacing the default linker script. Default linker scripts are stored in a system-\/specific location (e. g. under {\ttfamily /usr/local/avr/lib/ldscripts} on Unix systems), and consist of the A\+VR architecture name (avr2 through avr5) with the suffix {\ttfamily }.x appended. They describe how the various \mbox{\hyperlink{mem_sections}{memory sections}} will be linked together. \hypertarget{using_tools_using_pass_ld_opts}{}\doxysubsubsection{Passing linker options from the C compiler}\label{using_tools_using_pass_ld_opts}
By default, all unknown non-\/option arguments on the avr-\/gcc command-\/line (i. e., all filename arguments that don\textquotesingle{}t have a suffix that is handled by avr-\/gcc) are passed straight to the linker. Thus, all files ending in {\ttfamily }.o (object files) and {\ttfamily }.a (object libraries) are provided to the linker.

System libraries are usually not passed by their explicit filename but rather using the {\ttfamily -\/l} option which uses an abbreviated form of the archive filename (see above). avr-\/libc ships two system libraries, {\ttfamily libc.\+a}, and {\ttfamily libm.\+a}. While the standard library {\ttfamily libc.\+a} will always be searched for unresolved references when the linker is started using the C compiler frontend (i. e., there\textquotesingle{}s always at least one implied {\ttfamily -\/lc} option), the mathematics library {\ttfamily libm.\+a} needs to be explicitly requested using {\ttfamily -\/lm}. See also the \mbox{\hyperlink{FAQ_faq_libm}{entry in the F\+AQ}} explaining this.

Conventionally, Makefiles use the {\ttfamily make} macro {\ttfamily L\+D\+L\+I\+BS} to keep track of {\ttfamily -\/l} (and possibly {\ttfamily -\/L}) options that should only be appended to the C compiler command-\/line when linking the final binary. In contrast, the macro {\ttfamily L\+D\+F\+L\+A\+GS} is used to store other command-\/line options to the C compiler that should be passed as options during the linking stage. The difference is that options are placed early on the command-\/line, while libraries are put at the end since they are to be used to resolve global symbols that are still unresolved at this point.

Specific linker flags can be passed from the C compiler command-\/line using the {\ttfamily -\/Wl} compiler option, see \mbox{\hyperlink{using_tools_gcc_minusW}{above}}. This option requires that there be no spaces in the appended linker option, while some of the linker options above (like {\ttfamily -\/Map} or {\ttfamily --defsym}) would require a space. In these situations, the space can be replaced by an equal sign as well. For example, the following command-\/line can be used to compile {\ttfamily foo.\+c} into an executable, and also produce a link map that contains a cross-\/reference list in the file {\ttfamily foo.\+map\+:} 

\begin{DoxyVerb}	$ avr-gcc -O -o foo.out -Wl,-Map=foo.map -Wl,--cref foo.c
\end{DoxyVerb}


Alternatively, a comma as a placeholder will be replaced by a space before passing the option to the linker. So for a device with external S\+R\+AM, the following command-\/line would cause the linker to place the data segment at address 0x2000 in the S\+R\+AM\+:

\begin{DoxyVerb}	$ avr-gcc -mmcu=atmega128 -o foo.out -Wl,-Tdata,0x802000
\end{DoxyVerb}


See the explanation of the \mbox{\hyperlink{mem_sections_sec_dot_data}{data section}} for why 0x800000 needs to be added to the actual value. Note that the stack will still remain in internal R\+AM, through the symbol {\ttfamily \+\_\+\+\_\+stack} that is provided by the run-\/time startup code. This is probably a good idea anyway (since internal R\+AM access is faster), and even required for some early devices that had hardware bugs preventing them from using a stack in external R\+AM. Note also that the heap for {\ttfamily \mbox{\hyperlink{stdlib_8h_a4996af830ebe744d9678e5251dfd3ebd}{malloc()}}} will still be placed after all the variables in the data section, so in this situation, no stack/heap collision can occur.

In order to relocate the stack from its default location at the top of interns R\+AM, the value of the symbol {\ttfamily \+\_\+\+\_\+stack} can be changed on the linker command-\/line. As the linker is typically called from the compiler frontend, this can be achieved using a compiler option like


\begin{DoxyCode}{0}
\DoxyCodeLine{-\/Wl,-\/-\/defsym=\_\_stack=0x8003ff}
\end{DoxyCode}


The above will make the code use stack space from R\+AM address 0x3ff downwards. The amount of stack space available then depends on the bottom address of internal R\+AM for a particular device. It is the responsibility of the application to ensure the stack does not grow out of bounds, as well as to arrange for the stack to not collide with variable allocations made by the compiler (sections .data and .bss). 
