\hypertarget{group__avr__watchdog}{}\doxysubsection{$<$avr/wdt.h$>$\+: Watchdog timer handling}
\label{group__avr__watchdog}\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxysubsubsection*{Macros}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group__avr__watchdog_ga9e52c54d10b6a6a7ce04aaaa4abea51f}{wdt\+\_\+reset}}()~\+\_\+\+\_\+asm\+\_\+\+\_\+ \+\_\+\+\_\+volatile\+\_\+\+\_\+ (\char`\"{}wdr\char`\"{})
\item 
\#define \mbox{\hyperlink{group__avr__watchdog_gad45893280f49113ffc2e67e1d741f29d}{W\+D\+T\+O\+\_\+15\+MS}}~0
\item 
\#define \mbox{\hyperlink{group__avr__watchdog_ga057dd21dc54e71de0e20d8bd5734915d}{W\+D\+T\+O\+\_\+30\+MS}}~1
\item 
\#define \mbox{\hyperlink{group__avr__watchdog_ga7a5b072c51c05a34cc38111f0e6724e5}{W\+D\+T\+O\+\_\+60\+MS}}~2
\item 
\#define \mbox{\hyperlink{group__avr__watchdog_ga7d028bcdb4a4103549fc6fb4ec07fbcd}{W\+D\+T\+O\+\_\+120\+MS}}~3
\item 
\#define \mbox{\hyperlink{group__avr__watchdog_ga66d5f50cc76b92c76900d77ef577d53e}{W\+D\+T\+O\+\_\+250\+MS}}~4
\item 
\#define \mbox{\hyperlink{group__avr__watchdog_gacf89fc5fb6c8aa9efaadb86872cfbcdf}{W\+D\+T\+O\+\_\+500\+MS}}~5
\item 
\#define \mbox{\hyperlink{group__avr__watchdog_ga36302e15f38a4eeb8a328724bb8165e9}{W\+D\+T\+O\+\_\+1S}}~6
\item 
\#define \mbox{\hyperlink{group__avr__watchdog_ga05fc682d276a36d8cc4e9178340ff004}{W\+D\+T\+O\+\_\+2S}}~7
\item 
\#define \mbox{\hyperlink{group__avr__watchdog_ga752b0b1b5ba9009bc09976494313e30d}{W\+D\+T\+O\+\_\+4S}}~8
\item 
\#define \mbox{\hyperlink{group__avr__watchdog_gaf074e538b2a1d5031931530f29a09fce}{W\+D\+T\+O\+\_\+8S}}~9
\end{DoxyCompactItemize}
\doxysubsubsection*{Functions}
\begin{DoxyCompactItemize}
\item 
static \+\_\+\+\_\+inline\+\_\+\+\_\+ \mbox{\hyperlink{group__avr__watchdog_gadaa6dd28b5d08df35e49b1248d7e5fb0}{\+\_\+\+\_\+attribute\+\_\+\+\_\+}} ((\+\_\+\+\_\+always\+\_\+inline\+\_\+\+\_\+)) void wdt\+\_\+enable(const \mbox{\hyperlink{group__avr__stdint_gaba7bc1797add20fe3efdf37ced1182c5}{uint8\+\_\+t}} value)
\end{DoxyCompactItemize}


\doxysubsubsection{Detailed Description}

\begin{DoxyCode}{0}
\DoxyCodeLine{\textcolor{preprocessor}{\#include <\mbox{\hyperlink{wdt_8h}{avr/wdt.h}}>} }
\end{DoxyCode}


This header file declares the interface to some inline macros handling the watchdog timer present in many A\+VR devices. In order to prevent the watchdog timer configuration from being accidentally altered by a crashing application, a special timed sequence is required in order to change it. The macros within this header file handle the required sequence automatically before changing any value. Interrupts will be disabled during the manipulation.

\begin{DoxyNote}{Note}
Depending on the fuse configuration of the particular device, further restrictions might apply, in particular it might be disallowed to turn off the watchdog timer.
\end{DoxyNote}
Note that for newer devices (A\+Tmega88 and newer, effectively any A\+VR that has the option to also generate interrupts), the watchdog timer remains active even after a system reset (except a power-\/on condition), using the fastest prescaler value (approximately 15 ms). It is therefore required to turn off the watchdog early during program startup, the datasheet recommends a sequence like the following\+:


\begin{DoxyCode}{0}
\DoxyCodeLine{\textcolor{preprocessor}{\#include <\mbox{\hyperlink{stdint_8h}{stdint.h}}>}}
\DoxyCodeLine{\textcolor{preprocessor}{\#include <\mbox{\hyperlink{wdt_8h}{avr/wdt.h}}>}}
\DoxyCodeLine{}
\DoxyCodeLine{\mbox{\hyperlink{group__avr__stdint_gaba7bc1797add20fe3efdf37ced1182c5}{uint8\_t}} mcusr\_mirror \mbox{\hyperlink{power_8h_a577a0eebac2a6c2d105e61d9c8f04140}{\_\_attribute\_\_}} ((section (\textcolor{stringliteral}{".noinit"})));}
\DoxyCodeLine{}
\DoxyCodeLine{\textcolor{keywordtype}{void} get\_mcusr(\textcolor{keywordtype}{void}) \(\backslash\)}
\DoxyCodeLine{  \_\_attribute\_\_((naked)) \(\backslash\)}
\DoxyCodeLine{  \_\_attribute\_\_((section(\textcolor{stringliteral}{".init3"})));}
\DoxyCodeLine{\textcolor{keywordtype}{void} get\_mcusr(\textcolor{keywordtype}{void})}
\DoxyCodeLine{\{}
\DoxyCodeLine{  mcusr\_mirror = MCUSR;}
\DoxyCodeLine{  MCUSR = 0;}
\DoxyCodeLine{  wdt\_disable();}
\DoxyCodeLine{\}}
\end{DoxyCode}


Saving the value of M\+C\+U\+SR in {\ttfamily mcusr\+\_\+mirror} is only needed if the application later wants to examine the reset source, but in particular, clearing the watchdog reset flag before disabling the watchdog is required, according to the datasheet. 

\doxysubsubsection{Macro Definition Documentation}
\mbox{\Hypertarget{group__avr__watchdog_ga9e52c54d10b6a6a7ce04aaaa4abea51f}\label{group__avr__watchdog_ga9e52c54d10b6a6a7ce04aaaa4abea51f}} 
\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}!wdt\_reset@{wdt\_reset}}
\index{wdt\_reset@{wdt\_reset}!$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxyparagraph{\texorpdfstring{wdt\_reset}{wdt\_reset}}
{\footnotesize\ttfamily \#define wdt\+\_\+reset(\begin{DoxyParamCaption}{ }\end{DoxyParamCaption})~\+\_\+\+\_\+asm\+\_\+\+\_\+ \+\_\+\+\_\+volatile\+\_\+\+\_\+ (\char`\"{}wdr\char`\"{})}

Reset the watchdog timer. When the watchdog timer is enabled, a call to this instruction is required before the timer expires, otherwise a watchdog-\/initiated device reset will occur. \mbox{\Hypertarget{group__avr__watchdog_ga7d028bcdb4a4103549fc6fb4ec07fbcd}\label{group__avr__watchdog_ga7d028bcdb4a4103549fc6fb4ec07fbcd}} 
\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}!WDTO\_120MS@{WDTO\_120MS}}
\index{WDTO\_120MS@{WDTO\_120MS}!$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxyparagraph{\texorpdfstring{WDTO\_120MS}{WDTO\_120MS}}
{\footnotesize\ttfamily \#define W\+D\+T\+O\+\_\+120\+MS~3}

See {\ttfamily W\+D\+T\+O\+\_\+15\+MS} \mbox{\Hypertarget{group__avr__watchdog_gad45893280f49113ffc2e67e1d741f29d}\label{group__avr__watchdog_gad45893280f49113ffc2e67e1d741f29d}} 
\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}!WDTO\_15MS@{WDTO\_15MS}}
\index{WDTO\_15MS@{WDTO\_15MS}!$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxyparagraph{\texorpdfstring{WDTO\_15MS}{WDTO\_15MS}}
{\footnotesize\ttfamily \#define W\+D\+T\+O\+\_\+15\+MS~0}

Symbolic constants for the watchdog timeout. Since the watchdog timer is based on a free-\/running RC oscillator, the times are approximate only and apply to a supply voltage of 5 V. At lower supply voltages, the times will increase. For older devices, the times will be as large as three times when operating at Vcc = 3 V, while the newer devices (e. g. A\+Tmega128, A\+Tmega8) only experience a negligible change.

Possible timeout values are\+: 15 ms, 30 ms, 60 ms, 120 ms, 250 ms, 500 ms, 1 s, 2 s. (Some devices also allow for 4 s and 8 s.) Symbolic constants are formed by the prefix {\ttfamily W\+D\+T\+O\+\_\+}, followed by the time.

Example that would select a watchdog timer expiry of approximately 500 ms\+: 
\begin{DoxyCode}{0}
\DoxyCodeLine{wdt\_enable(\mbox{\hyperlink{group__avr__watchdog_gacf89fc5fb6c8aa9efaadb86872cfbcdf}{WDTO\_500MS}});}
\end{DoxyCode}
 \mbox{\Hypertarget{group__avr__watchdog_ga36302e15f38a4eeb8a328724bb8165e9}\label{group__avr__watchdog_ga36302e15f38a4eeb8a328724bb8165e9}} 
\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}!WDTO\_1S@{WDTO\_1S}}
\index{WDTO\_1S@{WDTO\_1S}!$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxyparagraph{\texorpdfstring{WDTO\_1S}{WDTO\_1S}}
{\footnotesize\ttfamily \#define W\+D\+T\+O\+\_\+1S~6}

See {\ttfamily W\+D\+T\+O\+\_\+15\+MS} \mbox{\Hypertarget{group__avr__watchdog_ga66d5f50cc76b92c76900d77ef577d53e}\label{group__avr__watchdog_ga66d5f50cc76b92c76900d77ef577d53e}} 
\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}!WDTO\_250MS@{WDTO\_250MS}}
\index{WDTO\_250MS@{WDTO\_250MS}!$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxyparagraph{\texorpdfstring{WDTO\_250MS}{WDTO\_250MS}}
{\footnotesize\ttfamily \#define W\+D\+T\+O\+\_\+250\+MS~4}

See {\ttfamily W\+D\+T\+O\+\_\+15\+MS} \mbox{\Hypertarget{group__avr__watchdog_ga05fc682d276a36d8cc4e9178340ff004}\label{group__avr__watchdog_ga05fc682d276a36d8cc4e9178340ff004}} 
\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}!WDTO\_2S@{WDTO\_2S}}
\index{WDTO\_2S@{WDTO\_2S}!$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxyparagraph{\texorpdfstring{WDTO\_2S}{WDTO\_2S}}
{\footnotesize\ttfamily \#define W\+D\+T\+O\+\_\+2S~7}

See {\ttfamily W\+D\+T\+O\+\_\+15\+MS} \mbox{\Hypertarget{group__avr__watchdog_ga057dd21dc54e71de0e20d8bd5734915d}\label{group__avr__watchdog_ga057dd21dc54e71de0e20d8bd5734915d}} 
\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}!WDTO\_30MS@{WDTO\_30MS}}
\index{WDTO\_30MS@{WDTO\_30MS}!$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxyparagraph{\texorpdfstring{WDTO\_30MS}{WDTO\_30MS}}
{\footnotesize\ttfamily \#define W\+D\+T\+O\+\_\+30\+MS~1}

See {\ttfamily W\+D\+T\+O\+\_\+15\+MS} \mbox{\Hypertarget{group__avr__watchdog_ga752b0b1b5ba9009bc09976494313e30d}\label{group__avr__watchdog_ga752b0b1b5ba9009bc09976494313e30d}} 
\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}!WDTO\_4S@{WDTO\_4S}}
\index{WDTO\_4S@{WDTO\_4S}!$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxyparagraph{\texorpdfstring{WDTO\_4S}{WDTO\_4S}}
{\footnotesize\ttfamily \#define W\+D\+T\+O\+\_\+4S~8}

See {\ttfamily W\+D\+T\+O\+\_\+15\+MS} Note\+: This is only available on the A\+Ttiny2313, A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny84A, A\+Ttiny25, A\+Ttiny45, A\+Ttiny85, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861, A\+Tmega48, A\+Tmega88, A\+Tmega168, A\+Tmega48P, A\+Tmega88P, A\+Tmega168P, A\+Tmega328P, A\+Tmega164P, A\+Tmega324P, A\+Tmega644P, A\+Tmega644, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega8\+H\+VA, A\+Tmega16\+H\+VA, A\+Tmega32\+H\+VB, A\+Tmega406, A\+Tmega1284P, A\+T90\+P\+W\+M1, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M2B, A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M3B, A\+T90\+P\+W\+M216, A\+T90\+P\+W\+M316, A\+T90\+P\+W\+M81, A\+T90\+P\+W\+M161, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B646, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B1287, A\+Ttiny48, A\+Ttiny88. \mbox{\Hypertarget{group__avr__watchdog_gacf89fc5fb6c8aa9efaadb86872cfbcdf}\label{group__avr__watchdog_gacf89fc5fb6c8aa9efaadb86872cfbcdf}} 
\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}!WDTO\_500MS@{WDTO\_500MS}}
\index{WDTO\_500MS@{WDTO\_500MS}!$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxyparagraph{\texorpdfstring{WDTO\_500MS}{WDTO\_500MS}}
{\footnotesize\ttfamily \#define W\+D\+T\+O\+\_\+500\+MS~5}

See {\ttfamily W\+D\+T\+O\+\_\+15\+MS} \mbox{\Hypertarget{group__avr__watchdog_ga7a5b072c51c05a34cc38111f0e6724e5}\label{group__avr__watchdog_ga7a5b072c51c05a34cc38111f0e6724e5}} 
\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}!WDTO\_60MS@{WDTO\_60MS}}
\index{WDTO\_60MS@{WDTO\_60MS}!$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxyparagraph{\texorpdfstring{WDTO\_60MS}{WDTO\_60MS}}
{\footnotesize\ttfamily \#define W\+D\+T\+O\+\_\+60\+MS~2}

See {\ttfamily W\+D\+T\+O\+\_\+15\+MS} \mbox{\Hypertarget{group__avr__watchdog_gaf074e538b2a1d5031931530f29a09fce}\label{group__avr__watchdog_gaf074e538b2a1d5031931530f29a09fce}} 
\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}!WDTO\_8S@{WDTO\_8S}}
\index{WDTO\_8S@{WDTO\_8S}!$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxyparagraph{\texorpdfstring{WDTO\_8S}{WDTO\_8S}}
{\footnotesize\ttfamily \#define W\+D\+T\+O\+\_\+8S~9}

See {\ttfamily W\+D\+T\+O\+\_\+15\+MS} Note\+: This is only available on the A\+Ttiny2313, A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny84A, A\+Ttiny25, A\+Ttiny45, A\+Ttiny85, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861, A\+Tmega48, A\+Tmega48A, A\+Tmega48\+PA, A\+Tmega88, A\+Tmega168, A\+Tmega48P, A\+Tmega88P, A\+Tmega168P, A\+Tmega328P, A\+Tmega164P, A\+Tmega324P, A\+Tmega644P, A\+Tmega644, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega8\+H\+VA, A\+Tmega16\+H\+VA, A\+Tmega32\+H\+VB, A\+Tmega406, A\+Tmega1284P, A\+Tmega2564\+R\+F\+R2, A\+Tmega256\+R\+F\+R2, A\+Tmega1284\+R\+F\+R2, A\+Tmega128\+R\+F\+R2, A\+Tmega644\+R\+F\+R2, A\+Tmega64\+R\+F\+R2 A\+T90\+P\+W\+M1, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M2B, A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M3B, A\+T90\+P\+W\+M216, A\+T90\+P\+W\+M316, A\+T90\+P\+W\+M81, A\+T90\+P\+W\+M161, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B646, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B1287, A\+Ttiny48, A\+Ttiny88, A\+Txmega16a4u, A\+Txmega32a4u, A\+Txmega16c4, A\+Txmega32c4, A\+Txmega128c3, A\+Txmega192c3, A\+Txmega256c3. 

\doxysubsubsection{Function Documentation}
\mbox{\Hypertarget{group__avr__watchdog_gadaa6dd28b5d08df35e49b1248d7e5fb0}\label{group__avr__watchdog_gadaa6dd28b5d08df35e49b1248d7e5fb0}} 
\index{$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}!\_\_attribute\_\_@{\_\_attribute\_\_}}
\index{\_\_attribute\_\_@{\_\_attribute\_\_}!$<$avr/wdt.h$>$: Watchdog timer handling@{$<$avr/wdt.h$>$: Watchdog timer handling}}
\doxyparagraph{\texorpdfstring{\_\_attribute\_\_()}{\_\_attribute\_\_()}}
{\footnotesize\ttfamily static \+\_\+\+\_\+inline\+\_\+\+\_\+ \+\_\+\+\_\+attribute\+\_\+\+\_\+ (\begin{DoxyParamCaption}\item[{(\+\_\+\+\_\+always\+\_\+inline\+\_\+\+\_\+)}]{ }\end{DoxyParamCaption}) const\hspace{0.3cm}{\ttfamily [static]}}

Enable the watchdog timer, configuring it for expiry after {\ttfamily timeout} (which is a combination of the {\ttfamily W\+D\+P0} through {\ttfamily W\+D\+P2} bits to write into the {\ttfamily W\+D\+T\+CR} register; For those devices that have a {\ttfamily W\+D\+T\+C\+SR} register, it uses the combination of the {\ttfamily W\+D\+P0} through {\ttfamily W\+D\+P3} bits).

See also the symbolic constants {\ttfamily W\+D\+T\+O\+\_\+15\+MS} et al. 