\hypertarget{group__avr__interrupts}{}\doxysubsection{$<$avr/interrupt.h$>$\+: Interrupts}
\label{group__avr__interrupts}\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxysubsubsection*{Global manipulation of the interrupt flag}
\label{_amgrp0c713759b89b91c30b92dfba7260e51f}%
The global interrupt flag is maintained in the I bit of the status register (S\+R\+EG).

Handling interrupts frequently requires attention regarding atomic access to objects that could be altered by code running within an interrupt context, see $<$\mbox{\hyperlink{atomic_8h}{util/atomic.\+h}}$>$.

Frequently, interrupts are being disabled for periods of time in order to perform certain operations without being disturbed; see \mbox{\hyperlink{optimization_optim_code_reorder}{Problems with reordering code}} for things to be taken into account with respect to compiler optimizations. \begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group__avr__interrupts_gaad5ebd34cb344c26ac87594f79b06b73}{sei}}()
\item 
\#define \mbox{\hyperlink{group__avr__interrupts_ga68c330e94fe121eba993e5a5973c3162}{cli}}()
\end{DoxyCompactItemize}
\doxysubsubsection*{Macros for writing interrupt handler functions}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{I\+SR}}(vector,  attributes)
\item 
\#define \mbox{\hyperlink{group__avr__interrupts_ga67cd0dea412157775c2f2a3ffe9fb8ff}{S\+I\+G\+N\+AL}}(vector)
\item 
\#define \mbox{\hyperlink{group__avr__interrupts_ga751c22101f7e8f2fbe792c64a81f8dba}{E\+M\+P\+T\+Y\+\_\+\+I\+N\+T\+E\+R\+R\+U\+PT}}(vector)
\item 
\#define \mbox{\hyperlink{group__avr__interrupts_gade46eb4e42cc9d56c19b1f91448f1b76}{I\+S\+R\+\_\+\+A\+L\+I\+AS}}(vector,  target\+\_\+vector)
\item 
\#define \mbox{\hyperlink{group__avr__interrupts_ga3b991e8168db8fc866e31f9a6d10533b}{reti}}()
\item 
\#define \mbox{\hyperlink{group__avr__interrupts_ga1f6459a85cda682b2163a20af03ac744}{B\+A\+D\+I\+S\+R\+\_\+vect}}
\end{DoxyCompactItemize}
\doxysubsubsection*{I\+SR attributes}
\begin{DoxyCompactItemize}
\item 
\#define \mbox{\hyperlink{group__avr__interrupts_ga5fc50a0507a58e16aca4c70345ddac6a}{I\+S\+R\+\_\+\+B\+L\+O\+CK}}
\item 
\#define \mbox{\hyperlink{group__avr__interrupts_ga44569cb914d2aaf8fbb436f8f7c4ca68}{I\+S\+R\+\_\+\+N\+O\+B\+L\+O\+CK}}
\item 
\#define \mbox{\hyperlink{group__avr__interrupts_ga8b4c7e44627db0a60d676213add42d64}{I\+S\+R\+\_\+\+N\+A\+K\+ED}}
\item 
\#define \mbox{\hyperlink{group__avr__interrupts_gaa87c0c624b62f40a17539be6946c3e26}{I\+S\+R\+\_\+\+A\+L\+I\+A\+S\+OF}}(target\+\_\+vector)
\end{DoxyCompactItemize}


\doxysubsubsection{Detailed Description}
\begin{DoxyNote}{Note}
This discussion of interrupts was originally taken from Rich Neswold\textquotesingle{}s document. See \mbox{\hyperlink{acks}{Acknowledgments}}.
\end{DoxyNote}
\doxysubparagraph*{Introduction to avr-\/libc\textquotesingle{}s interrupt handling}

It\textquotesingle{}s nearly impossible to find compilers that agree on how to handle interrupt code. Since the C language tries to stay away from machine dependent details, each compiler writer is forced to design their method of support.

In the A\+V\+R-\/\+G\+CC environment, the vector table is predefined to point to interrupt routines with predetermined names. By using the appropriate name, your routine will be called when the corresponding interrupt occurs. The device library provides a set of default interrupt routines, which will get used if you don\textquotesingle{}t define your own.

Patching into the vector table is only one part of the problem. The compiler uses, by convention, a set of registers when it\textquotesingle{}s normally executing compiler-\/generated code. It\textquotesingle{}s important that these registers, as well as the status register, get saved and restored. The extra code needed to do this is enabled by tagging the interrupt function with {\ttfamily \+\_\+\+\_\+attribute\+\_\+\+\_\+((signal))}.

These details seem to make interrupt routines a little messy, but all these details are handled by the Interrupt A\+PI. An interrupt routine is defined with \mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{I\+S\+R()}}. This macro register and mark the routine as an interrupt handler for the specified peripheral. The following is an example definition of a handler for the A\+DC interrupt.


\begin{DoxyCode}{0}
\DoxyCodeLine{\textcolor{preprocessor}{\#include <\mbox{\hyperlink{interrupt_8h}{avr/interrupt.h}}>}}
\DoxyCodeLine{}
\DoxyCodeLine{\mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{ISR}}(ADC\_vect)}
\DoxyCodeLine{\{}
\DoxyCodeLine{    \textcolor{comment}{// user code here}}
\DoxyCodeLine{\}}
\end{DoxyCode}


Refer to the chapter explaining \mbox{\hyperlink{assembler_ass_isr}{assembler programming}} for an explanation about interrupt routines written solely in assembler language.

\doxysubparagraph*{Catch-\/all interrupt vector}

If an unexpected interrupt occurs (interrupt is enabled and no handler is installed, which usually indicates a bug), then the default action is to reset the device by jumping to the reset vector. You can override this by supplying a function named {\ttfamily B\+A\+D\+I\+S\+R\+\_\+vect} which should be defined with \mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{I\+S\+R()}} as such. (The name B\+A\+D\+I\+S\+R\+\_\+vect is actually an alias for \+\_\+\+\_\+vector\+\_\+default. The latter must be used inside assembly code in case $<$\mbox{\hyperlink{interrupt_8h}{avr/interrupt.\+h}}$>$ is not included.)


\begin{DoxyCode}{0}
\DoxyCodeLine{\textcolor{preprocessor}{\#include <\mbox{\hyperlink{interrupt_8h}{avr/interrupt.h}}>}}
\DoxyCodeLine{}
\DoxyCodeLine{\mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{ISR}}(\mbox{\hyperlink{group__avr__interrupts_ga1f6459a85cda682b2163a20af03ac744}{BADISR\_vect}})}
\DoxyCodeLine{\{}
\DoxyCodeLine{    \textcolor{comment}{// user code here}}
\DoxyCodeLine{\}}
\end{DoxyCode}


\doxysubparagraph*{Nested interrupts}

The A\+VR hardware clears the global interrupt flag in S\+R\+EG before entering an interrupt vector. Thus, normally interrupts will remain disabled inside the handler until the handler exits, where the R\+E\+TI instruction (that is emitted by the compiler as part of the normal function epilogue for an interrupt handler) will eventually re-\/enable further interrupts. For that reason, interrupt handlers normally do not nest. For most interrupt handlers, this is the desired behaviour, for some it is even required in order to prevent infinitely recursive interrupts (like U\+A\+RT interrupts, or level-\/triggered external interrupts). In rare circumstances though it might be desired to re-\/enable the global interrupt flag as early as possible in the interrupt handler, in order to not defer any other interrupt more than absolutely needed. This could be done using an \mbox{\hyperlink{group__avr__interrupts_gaad5ebd34cb344c26ac87594f79b06b73}{sei()}} instruction right at the beginning of the interrupt handler, but this still leaves few instructions inside the compiler-\/generated function prologue to run with global interrupts disabled. The compiler can be instructed to insert an S\+EI instruction right at the beginning of an interrupt handler by declaring the handler the following way\+:

\label{group__avr__interrupts_attr_interrupt}%
\Hypertarget{group__avr__interrupts_attr_interrupt}%

\begin{DoxyCode}{0}
\DoxyCodeLine{\mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{ISR}}(XXX\_vect, \mbox{\hyperlink{group__avr__interrupts_ga44569cb914d2aaf8fbb436f8f7c4ca68}{ISR\_NOBLOCK}})}
\DoxyCodeLine{\{}
\DoxyCodeLine{  ...}
\DoxyCodeLine{\}}
\end{DoxyCode}


where {\ttfamily X\+X\+X\+\_\+vect} is the name of a valid interrupt vector for the M\+CU type in question, as explained below.

\doxysubparagraph*{Two vectors sharing the same code}

In some circumstances, the actions to be taken upon two different interrupts might be completely identical so a single implementation for the I\+SR would suffice. For example, pin-\/change interrupts arriving from two different ports could logically signal an event that is independent from the actual port (and thus interrupt vector) where it happened. Sharing interrupt vector code can be accomplished using the \mbox{\hyperlink{group__avr__interrupts_gaa87c0c624b62f40a17539be6946c3e26}{I\+S\+R\+\_\+\+A\+L\+I\+A\+S\+O\+F()}} attribute to the I\+SR macro\+:


\begin{DoxyCode}{0}
\DoxyCodeLine{\mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{ISR}}(PCINT0\_vect)}
\DoxyCodeLine{\{}
\DoxyCodeLine{  ...}
\DoxyCodeLine{  \textcolor{comment}{// Code to handle the event.}}
\DoxyCodeLine{\}}
\DoxyCodeLine{}
\DoxyCodeLine{\mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{ISR}}(PCINT1\_vect, \mbox{\hyperlink{group__avr__interrupts_gaa87c0c624b62f40a17539be6946c3e26}{ISR\_ALIASOF}}(PCINT0\_vect));}
\end{DoxyCode}


\begin{DoxyNote}{Note}
There is no body to the aliased I\+SR.
\end{DoxyNote}
Note that the \mbox{\hyperlink{group__avr__interrupts_gaa87c0c624b62f40a17539be6946c3e26}{I\+S\+R\+\_\+\+A\+L\+I\+A\+S\+O\+F()}} feature requires G\+CC 4.\+2 or above (or a patched version of G\+CC 4.\+1.\+x). See the documentation of the \mbox{\hyperlink{group__avr__interrupts_gade46eb4e42cc9d56c19b1f91448f1b76}{I\+S\+R\+\_\+\+A\+L\+I\+A\+S()}} macro for an implementation which is less elegant but could be applied to all compiler versions.

\doxysubparagraph*{Empty interrupt service routines}

In rare circumstances, in interrupt vector does not need any code to be implemented at all. The vector must be declared anyway, so when the interrupt triggers it won\textquotesingle{}t execute the B\+A\+D\+I\+S\+R\+\_\+vect code (which by default restarts the application).

This could for example be the case for interrupts that are solely enabled for the purpose of getting the controller out of \mbox{\hyperlink{group__avr__sleep_ga3775b21f297187752bcfc434a541209a}{sleep\+\_\+mode()}}.

A handler for such an interrupt vector can be declared using the \mbox{\hyperlink{group__avr__interrupts_ga751c22101f7e8f2fbe792c64a81f8dba}{E\+M\+P\+T\+Y\+\_\+\+I\+N\+T\+E\+R\+R\+U\+P\+T()}} macro\+:


\begin{DoxyCode}{0}
\DoxyCodeLine{\mbox{\hyperlink{group__avr__interrupts_ga751c22101f7e8f2fbe792c64a81f8dba}{EMPTY\_INTERRUPT}}(ADC\_vect);}
\end{DoxyCode}


\begin{DoxyNote}{Note}
There is no body to this macro.
\end{DoxyNote}
\doxysubparagraph*{Manually defined I\+S\+Rs}

In some circumstances, the compiler-\/generated prologue and epilogue of the I\+SR might not be optimal for the job, and a manually defined I\+SR could be considered particularly to speedup the interrupt handling.

One solution to this could be to implement the entire I\+SR as manual assembly code in a separate (assembly) file. See \mbox{\hyperlink{group__asmdemo}{Combining C and assembly source files}} for an example of how to implement it that way.

Another solution is to still implement the I\+SR in C language but take over the compiler\textquotesingle{}s job of generating the prologue and epilogue. This can be done using the I\+S\+R\+\_\+\+N\+A\+K\+ED attribute to the \mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{I\+S\+R()}} macro. Note that the compiler does not generate {\itshape anything} as prologue or epilogue, so the final \mbox{\hyperlink{group__avr__interrupts_ga3b991e8168db8fc866e31f9a6d10533b}{reti()}} must be provided by the actual implementation. S\+R\+EG must be manually saved if the I\+SR code modifies it, and the compiler-\/implied assumption of {\ttfamily \+\_\+\+\_\+zero\+\_\+reg\+\_\+\+\_\+} always being 0 could be wrong (e. g. when interrupting right after of a M\+UL instruction).


\begin{DoxyCode}{0}
\DoxyCodeLine{\mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{ISR}}(TIMER1\_OVF\_vect, \mbox{\hyperlink{group__avr__interrupts_ga8b4c7e44627db0a60d676213add42d64}{ISR\_NAKED}})}
\DoxyCodeLine{\{}
\DoxyCodeLine{  PORTB |= \mbox{\hyperlink{group__avr__sfr_ga11643f271076024c395a93800b3d9546}{\_BV}}(0);  \textcolor{comment}{// results in SBI which does not affect SREG}}
\DoxyCodeLine{  \mbox{\hyperlink{group__avr__interrupts_ga3b991e8168db8fc866e31f9a6d10533b}{reti}}();}
\DoxyCodeLine{\}}
\end{DoxyCode}


\doxysubparagraph*{Choosing the vector\+: Interrupt vector names}

The interrupt is chosen by supplying one of the symbols in following table.

There are currently two different styles present for naming the vectors. One form uses names starting with {\ttfamily S\+I\+G\+\_\+}, followed by a relatively verbose but arbitrarily chosen name describing the interrupt vector. This has been the only available style in avr-\/libc up to version 1.\+2.\+x.

Starting with avr-\/libc version 1.\+4.\+0, a second style of interrupt vector names has been added, where a short phrase for the vector description is followed by {\ttfamily \+\_\+vect}. The short phrase matches the vector name as described in the datasheet of the respective device (and in Atmel\textquotesingle{}s X\+ML files), with spaces replaced by an underscore and other non-\/alphanumeric characters dropped. Using the suffix {\ttfamily \+\_\+vect} is intented to improve portability to other C compilers available for the A\+VR that use a similar naming convention.

The historical naming style might become deprecated in a future release, so it is not recommended for new projects.

\begin{DoxyNote}{Note}
The \mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{I\+S\+R()}} macro cannot really spell-\/check the argument passed to them. Thus, by misspelling one of the names below in a call to \mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{I\+S\+R()}}, a function will be created that, while possibly being usable as an interrupt function, is not actually wired into the interrupt vector table. The compiler will generate a warning if it detects a suspiciously looking name of a \mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{I\+S\+R()}} function (i.\+e. one that after macro replacement does not start with \char`\"{}\+\_\+\+\_\+vector\+\_\+\char`\"{}).
\end{DoxyNote}
\label{group__avr__interrupts_avr_signames}%
\Hypertarget{group__avr__interrupts_avr_signames}%

\footnotesize  \tabulinesep=1mm
\begin{longtabu}spread 0pt [c]{*{4}{|X[-1]}|}
\hline
{\bfseries{Vector name}} &{\bfseries{Old vector name}} &{\bfseries{Description}} &{\bfseries{Applicable for device}} 

\\\cline{1-4}
A\+D\+C\+\_\+vect &S\+I\+G\+\_\+\+A\+DC &A\+DC Conversion Complete &A\+T90\+S2333, A\+T90\+S4433, A\+T90\+S4434, A\+T90\+S8535, A\+T90\+P\+W\+M216, A\+T90\+P\+W\+M2B, A\+T90\+P\+W\+M316, A\+T90\+P\+W\+M3B, A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega16, A\+Tmega163, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega32, A\+Tmega323, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega48P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega8, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Ttiny13, A\+Ttiny15, A\+Ttiny26, A\+Ttiny43U, A\+Ttiny48, A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
A\+N\+A\+L\+O\+G\+\_\+\+C\+O\+M\+P\+\_\+0\+\_\+vect &S\+I\+G\+\_\+\+C\+O\+M\+P\+A\+R\+A\+T\+O\+R0 &Analog Comparator 0 &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1  \\\cline{1-4}
A\+N\+A\+L\+O\+G\+\_\+\+C\+O\+M\+P\+\_\+1\+\_\+vect &S\+I\+G\+\_\+\+C\+O\+M\+P\+A\+R\+A\+T\+O\+R1 &Analog Comparator 1 &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1  \\\cline{1-4}
A\+N\+A\+L\+O\+G\+\_\+\+C\+O\+M\+P\+\_\+2\+\_\+vect &S\+I\+G\+\_\+\+C\+O\+M\+P\+A\+R\+A\+T\+O\+R2 &Analog Comparator 2 &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1  \\\cline{1-4}
A\+N\+A\+L\+O\+G\+\_\+\+C\+O\+M\+P\+\_\+vect &S\+I\+G\+\_\+\+C\+O\+M\+P\+A\+R\+A\+T\+OR &Analog Comparator &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega48P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
A\+N\+A\+\_\+\+C\+O\+M\+P\+\_\+vect &S\+I\+G\+\_\+\+C\+O\+M\+P\+A\+R\+A\+T\+OR &Analog Comparator &A\+T90\+S1200, A\+T90\+S2313, A\+T90\+S2333, A\+T90\+S4414, A\+T90\+S4433, A\+T90\+S4434, A\+T90\+S8515, A\+T90\+S8535, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega163, A\+Tmega32, A\+Tmega323, A\+Tmega8, A\+Tmega8515, A\+Tmega8535, A\+Ttiny11, A\+Ttiny12, A\+Ttiny13, A\+Ttiny15, A\+Ttiny2313, A\+Ttiny26, A\+Ttiny28, A\+Ttiny43U, A\+Ttiny48, A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861  \\\cline{1-4}
C\+A\+N\+I\+T\+\_\+vect &S\+I\+G\+\_\+\+C\+A\+N\+\_\+\+I\+N\+T\+E\+R\+R\+U\+P\+T1 &C\+AN Transfer Complete or Error &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64  \\\cline{1-4}
E\+E\+P\+R\+O\+M\+\_\+\+R\+E\+A\+D\+Y\+\_\+vect &S\+I\+G\+\_\+\+E\+E\+P\+R\+O\+M\+\_\+\+R\+E\+A\+DY, S\+I\+G\+\_\+\+E\+E\+\_\+\+R\+E\+A\+DY &&A\+Ttiny2313  \\\cline{1-4}
E\+E\+\_\+\+R\+D\+Y\+\_\+vect &S\+I\+G\+\_\+\+E\+E\+P\+R\+O\+M\+\_\+\+R\+E\+A\+DY &E\+E\+P\+R\+OM Ready &A\+T90\+S2333, A\+T90\+S4433, A\+T90\+S4434, A\+T90\+S8535, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega163, A\+Tmega32, A\+Tmega323, A\+Tmega8, A\+Tmega8515, A\+Tmega8535, A\+Ttiny12, A\+Ttiny13, A\+Ttiny15, A\+Ttiny26, A\+Ttiny43U, A\+Ttiny48, A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861  \\\cline{1-4}
E\+E\+\_\+\+R\+E\+A\+D\+Y\+\_\+vect &S\+I\+G\+\_\+\+E\+E\+P\+R\+O\+M\+\_\+\+R\+E\+A\+DY &E\+E\+P\+R\+OM Ready &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega32\+H\+VB, A\+Tmega406, A\+Tmega48P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Tmega16\+H\+VA, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
E\+X\+T\+\_\+\+I\+N\+T0\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+T\+E\+R\+R\+U\+P\+T0 &External Interrupt Request 0 &A\+Ttiny24, A\+Ttiny44, A\+Ttiny84  \\\cline{1-4}
I\+N\+T0\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+T\+E\+R\+R\+U\+P\+T0 &External Interrupt 0 &A\+T90\+S1200, A\+T90\+S2313, A\+T90\+S2323, A\+T90\+S2333, A\+T90\+S2343, A\+T90\+S4414, A\+T90\+S4433, A\+T90\+S4434, A\+T90\+S8515, A\+T90\+S8535, A\+T90\+P\+W\+M216, A\+T90\+P\+W\+M2B, A\+T90\+P\+W\+M316, A\+T90\+P\+W\+M3B, A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega163, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega32, A\+Tmega323, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega32\+H\+VB, A\+Tmega406, A\+Tmega48P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega8, A\+Tmega8515, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Tmega16\+H\+VA, A\+Ttiny11, A\+Ttiny12, A\+Ttiny13, A\+Ttiny15, A\+Ttiny22, A\+Ttiny2313, A\+Ttiny26, A\+Ttiny28, A\+Ttiny43U, A\+Ttiny48, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
I\+N\+T1\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+T\+E\+R\+R\+U\+P\+T1 &External Interrupt Request 1 &A\+T90\+S2313, A\+T90\+S2333, A\+T90\+S4414, A\+T90\+S4433, A\+T90\+S4434, A\+T90\+S8515, A\+T90\+S8535, A\+T90\+P\+W\+M216, A\+T90\+P\+W\+M2B, A\+T90\+P\+W\+M316, A\+T90\+P\+W\+M3B, A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega163, A\+Tmega168P, A\+Tmega32, A\+Tmega323, A\+Tmega328P, A\+Tmega32\+H\+VB, A\+Tmega406, A\+Tmega48P, A\+Tmega64, A\+Tmega8, A\+Tmega8515, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Tmega16\+H\+VA, A\+Ttiny2313, A\+Ttiny28, A\+Ttiny48, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
I\+N\+T2\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+T\+E\+R\+R\+U\+P\+T2 &External Interrupt Request 2 &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega32, A\+Tmega323, A\+Tmega32\+H\+VB, A\+Tmega406, A\+Tmega64, A\+Tmega8515, A\+Tmega8535, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Tmega16\+H\+VA, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
I\+N\+T3\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+T\+E\+R\+R\+U\+P\+T3 &External Interrupt Request 3 &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega32\+H\+VB, A\+Tmega406, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
I\+N\+T4\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+T\+E\+R\+R\+U\+P\+T4 &External Interrupt Request 4 &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
I\+N\+T5\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+T\+E\+R\+R\+U\+P\+T5 &External Interrupt Request 5 &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
I\+N\+T6\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+T\+E\+R\+R\+U\+P\+T6 &External Interrupt Request 6 &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
I\+N\+T7\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+T\+E\+R\+R\+U\+P\+T7 &External Interrupt Request 7 &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
I\+O\+\_\+\+P\+I\+N\+S\+\_\+vect &S\+I\+G\+\_\+\+P\+IN, S\+I\+G\+\_\+\+P\+I\+N\+\_\+\+C\+H\+A\+N\+GE &External Interrupt Request 0 &A\+Ttiny11, A\+Ttiny12, A\+Ttiny15, A\+Ttiny26  \\\cline{1-4}
L\+C\+D\+\_\+vect &S\+I\+G\+\_\+\+L\+CD &L\+CD Start of Frame &A\+Tmega169, A\+Tmega169P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega649, A\+Tmega6490  \\\cline{1-4}
L\+O\+W\+L\+E\+V\+E\+L\+\_\+\+I\+O\+\_\+\+P\+I\+N\+S\+\_\+vect &S\+I\+G\+\_\+\+P\+IN &Low-\/level Input on Port B &A\+Ttiny28  \\\cline{1-4}
O\+V\+R\+I\+T\+\_\+vect &S\+I\+G\+\_\+\+C\+A\+N\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W1 &C\+AN Timer Overrun &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64  \\\cline{1-4}
P\+C\+I\+N\+T0\+\_\+vect &S\+I\+G\+\_\+\+P\+I\+N\+\_\+\+C\+H\+A\+N\+G\+E0 &Pin Change Interrupt Request 0 &A\+Tmega162, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega32\+H\+VB, A\+Tmega406, A\+Tmega48P, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Ttiny13, A\+Ttiny43U, A\+Ttiny48, A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
P\+C\+I\+N\+T1\+\_\+vect &S\+I\+G\+\_\+\+P\+I\+N\+\_\+\+C\+H\+A\+N\+G\+E1 &Pin Change Interrupt Request 1 &A\+Tmega162, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega32\+H\+VB, A\+Tmega406, A\+Tmega48P, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Ttiny43U, A\+Ttiny48, A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82  \\\cline{1-4}
P\+C\+I\+N\+T2\+\_\+vect &S\+I\+G\+\_\+\+P\+I\+N\+\_\+\+C\+H\+A\+N\+G\+E2 &Pin Change Interrupt Request 2 &A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega3290, A\+Tmega3290P, A\+Tmega48P, A\+Tmega6450, A\+Tmega6490, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Ttiny48  \\\cline{1-4}
P\+C\+I\+N\+T3\+\_\+vect &S\+I\+G\+\_\+\+P\+I\+N\+\_\+\+C\+H\+A\+N\+G\+E3 &Pin Change Interrupt Request 3 &A\+Tmega3250, A\+Tmega3250P, A\+Tmega3290, A\+Tmega3290P, A\+Tmega6450, A\+Tmega6490, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Ttiny48  \\\cline{1-4}
P\+C\+I\+N\+T\+\_\+vect &S\+I\+G\+\_\+\+P\+I\+N\+\_\+\+C\+H\+A\+N\+GE, S\+I\+G\+\_\+\+P\+C\+I\+NT &&A\+Ttiny2313, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861  \\\cline{1-4}
P\+S\+C0\+\_\+\+C\+A\+P\+T\+\_\+vect &S\+I\+G\+\_\+\+P\+S\+C0\+\_\+\+C\+A\+P\+T\+U\+RE &P\+S\+C0 Capture Event &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1  \\\cline{1-4}
P\+S\+C0\+\_\+\+E\+C\+\_\+vect &S\+I\+G\+\_\+\+P\+S\+C0\+\_\+\+E\+N\+D\+\_\+\+C\+Y\+C\+LE &P\+S\+C0 End Cycle &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1  \\\cline{1-4}
P\+S\+C1\+\_\+\+C\+A\+P\+T\+\_\+vect &S\+I\+G\+\_\+\+P\+S\+C1\+\_\+\+C\+A\+P\+T\+U\+RE &P\+S\+C1 Capture Event &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1  \\\cline{1-4}
P\+S\+C1\+\_\+\+E\+C\+\_\+vect &S\+I\+G\+\_\+\+P\+S\+C1\+\_\+\+E\+N\+D\+\_\+\+C\+Y\+C\+LE &P\+S\+C1 End Cycle &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1  \\\cline{1-4}
P\+S\+C2\+\_\+\+C\+A\+P\+T\+\_\+vect &S\+I\+G\+\_\+\+P\+S\+C2\+\_\+\+C\+A\+P\+T\+U\+RE &P\+S\+C2 Capture Event &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1  \\\cline{1-4}
P\+S\+C2\+\_\+\+E\+C\+\_\+vect &S\+I\+G\+\_\+\+P\+S\+C2\+\_\+\+E\+N\+D\+\_\+\+C\+Y\+C\+LE &P\+S\+C2 End Cycle &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1  \\\cline{1-4}
S\+P\+I\+\_\+\+S\+T\+C\+\_\+vect &S\+I\+G\+\_\+\+S\+PI &Serial Transfer Complete &A\+T90\+S2333, A\+T90\+S4414, A\+T90\+S4433, A\+T90\+S4434, A\+T90\+S8515, A\+T90\+S8535, A\+T90\+P\+W\+M216, A\+T90\+P\+W\+M2B, A\+T90\+P\+W\+M316, A\+T90\+P\+W\+M3B, A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega163, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega32, A\+Tmega323, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega32\+H\+VB, A\+Tmega48P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega8, A\+Tmega8515, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Tmega16\+H\+VA, A\+Ttiny48, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
S\+P\+M\+\_\+\+R\+D\+Y\+\_\+vect &S\+I\+G\+\_\+\+S\+P\+M\+\_\+\+R\+E\+A\+DY &Store Program Memory Ready &A\+Tmega16, A\+Tmega162, A\+Tmega32, A\+Tmega323, A\+Tmega8, A\+Tmega8515, A\+Tmega8535  \\\cline{1-4}
S\+P\+M\+\_\+\+R\+E\+A\+D\+Y\+\_\+vect &S\+I\+G\+\_\+\+S\+P\+M\+\_\+\+R\+E\+A\+DY &Store Program Memory Read &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega1284P, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega406, A\+Tmega48P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M0\+\_\+\+C\+O\+M\+P\+A\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E0A &Timer/\+Counter Compare Match A &A\+Ttiny13, A\+Ttiny43U, A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85  \\\cline{1-4}
T\+I\+M0\+\_\+\+C\+O\+M\+P\+B\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E0B &Timer/\+Counter Compare Match B &A\+Ttiny13, A\+Ttiny43U, A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85  \\\cline{1-4}
T\+I\+M0\+\_\+\+O\+V\+F\+\_\+vect &S\+I\+G\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W0 &Timer/\+Counter0 Overflow &A\+Ttiny13, A\+Ttiny43U, A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85  \\\cline{1-4}
T\+I\+M1\+\_\+\+C\+A\+P\+T\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+P\+U\+T\+\_\+\+C\+A\+P\+T\+U\+R\+E1 &Timer/\+Counter1 Capture Event &A\+Ttiny24, A\+Ttiny44, A\+Ttiny84  \\\cline{1-4}
T\+I\+M1\+\_\+\+C\+O\+M\+P\+A\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E1A &Timer/\+Counter1 Compare Match A &A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85  \\\cline{1-4}
T\+I\+M1\+\_\+\+C\+O\+M\+P\+B\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E1B &Timer/\+Counter1 Compare Match B &A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85  \\\cline{1-4}
T\+I\+M1\+\_\+\+O\+V\+F\+\_\+vect &S\+I\+G\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W1 &Timer/\+Counter1 Overflow &A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85  \\\cline{1-4}
T\+I\+M\+E\+R0\+\_\+\+C\+A\+P\+T\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+P\+U\+T\+\_\+\+C\+A\+P\+T\+U\+R\+E0 &A\+DC Conversion Complete &A\+Ttiny261, A\+Ttiny461, A\+Ttiny861  \\\cline{1-4}
T\+I\+M\+E\+R0\+\_\+\+C\+O\+M\+P\+A\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E0A &Timer\+Counter0 Compare Match A &A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Tmega16\+H\+VA, A\+Ttiny2313, A\+Ttiny48, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R0\+\_\+\+C\+O\+M\+P\+B\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E0B, S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E0\+\_\+B &Timer Counter 0 Compare Match B &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+Tmega1284P, A\+Tmega168P, A\+Tmega328P, A\+Tmega32\+H\+VB, A\+Tmega48P, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Tmega16\+H\+VA, A\+Ttiny2313, A\+Ttiny48, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R0\+\_\+\+C\+O\+M\+P\+\_\+\+A\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E0A, S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E0\+\_\+A &Timer/\+Counter0 Compare Match A &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1  \\\cline{1-4}
T\+I\+M\+E\+R0\+\_\+\+C\+O\+M\+P\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E0 &Timer/\+Counter0 Compare Match &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega165, A\+Tmega165P, A\+Tmega169, A\+Tmega169P, A\+Tmega32, A\+Tmega323, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega8515, A\+Tmega8535  \\\cline{1-4}
T\+I\+M\+E\+R0\+\_\+\+O\+V\+F0\+\_\+vect &S\+I\+G\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W0 &Timer/\+Counter0 Overflow &A\+T90\+S2313, A\+T90\+S2323, A\+T90\+S2343, A\+Ttiny22, A\+Ttiny26  \\\cline{1-4}
T\+I\+M\+E\+R0\+\_\+\+O\+V\+F\+\_\+vect &S\+I\+G\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W0 &Timer/\+Counter0 Overflow &A\+T90\+S1200, A\+T90\+S2333, A\+T90\+S4414, A\+T90\+S4433, A\+T90\+S4434, A\+T90\+S8515, A\+T90\+S8535, A\+T90\+P\+W\+M216, A\+T90\+P\+W\+M2B, A\+T90\+P\+W\+M316, A\+T90\+P\+W\+M3B, A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega163, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega32, A\+Tmega323, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega32\+H\+VB, A\+Tmega48P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega8, A\+Tmega8515, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Tmega16\+H\+VA, A\+Ttiny11, A\+Ttiny12, A\+Ttiny15, A\+Ttiny2313, A\+Ttiny28, A\+Ttiny48, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R1\+\_\+\+C\+A\+P\+T1\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+P\+U\+T\+\_\+\+C\+A\+P\+T\+U\+R\+E1 &Timer/\+Counter1 Capture Event &A\+T90\+S2313  \\\cline{1-4}
T\+I\+M\+E\+R1\+\_\+\+C\+A\+P\+T\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+P\+U\+T\+\_\+\+C\+A\+P\+T\+U\+R\+E1 &Timer/\+Counter Capture Event &A\+T90\+S2333, A\+T90\+S4414, A\+T90\+S4433, A\+T90\+S4434, A\+T90\+S8515, A\+T90\+S8535, A\+T90\+P\+W\+M216, A\+T90\+P\+W\+M2B, A\+T90\+P\+W\+M316, A\+T90\+P\+W\+M3B, A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega163, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega32, A\+Tmega323, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega48P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega8, A\+Tmega8515, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Ttiny2313, A\+Ttiny48, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R1\+\_\+\+C\+M\+P\+A\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E1A &Timer/\+Counter1 Compare Match 1A &A\+Ttiny26  \\\cline{1-4}
T\+I\+M\+E\+R1\+\_\+\+C\+M\+P\+B\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E1B &Timer/\+Counter1 Compare Match 1B &A\+Ttiny26  \\\cline{1-4}
T\+I\+M\+E\+R1\+\_\+\+C\+O\+M\+P1\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E1A &Timer/\+Counter1 Compare Match &A\+T90\+S2313  \\\cline{1-4}
T\+I\+M\+E\+R1\+\_\+\+C\+O\+M\+P\+A\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E1A &Timer/\+Counter1 Compare Match A &A\+T90\+S4414, A\+T90\+S4434, A\+T90\+S8515, A\+T90\+S8535, A\+T90\+P\+W\+M216, A\+T90\+P\+W\+M2B, A\+T90\+P\+W\+M316, A\+T90\+P\+W\+M3B, A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega163, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega32, A\+Tmega323, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega32\+H\+VB, A\+Tmega48P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega8, A\+Tmega8515, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Tmega16\+H\+VA, A\+Ttiny2313, A\+Ttiny48, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R1\+\_\+\+C\+O\+M\+P\+B\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E1B &Timer/\+Counter1 Compare MatchB &A\+T90\+S4414, A\+T90\+S4434, A\+T90\+S8515, A\+T90\+S8535, A\+T90\+P\+W\+M216, A\+T90\+P\+W\+M2B, A\+T90\+P\+W\+M316, A\+T90\+P\+W\+M3B, A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega163, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega32, A\+Tmega323, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega32\+H\+VB, A\+Tmega48P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega8, A\+Tmega8515, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Tmega16\+H\+VA, A\+Ttiny2313, A\+Ttiny48, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R1\+\_\+\+C\+O\+M\+P\+C\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E1C &Timer/\+Counter1 Compare Match C &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R1\+\_\+\+C\+O\+M\+P\+D\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E0D &Timer/\+Counter1 Compare Match D &A\+Ttiny261, A\+Ttiny461, A\+Ttiny861  \\\cline{1-4}
T\+I\+M\+E\+R1\+\_\+\+C\+O\+M\+P\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E1A &Timer/\+Counter1 Compare Match &A\+T90\+S2333, A\+T90\+S4433, A\+Ttiny15  \\\cline{1-4}
T\+I\+M\+E\+R1\+\_\+\+O\+V\+F1\+\_\+vect &S\+I\+G\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W1 &Timer/\+Counter1 Overflow &A\+T90\+S2313, A\+Ttiny26  \\\cline{1-4}
T\+I\+M\+E\+R1\+\_\+\+O\+V\+F\+\_\+vect &S\+I\+G\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W1 &Timer/\+Counter1 Overflow &A\+T90\+S2333, A\+T90\+S4414, A\+T90\+S4433, A\+T90\+S4434, A\+T90\+S8515, A\+T90\+S8535, A\+T90\+P\+W\+M216, A\+T90\+P\+W\+M2B, A\+T90\+P\+W\+M316, A\+T90\+P\+W\+M3B, A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega163, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega32, A\+Tmega323, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega32\+H\+VB, A\+Tmega48P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega8, A\+Tmega8515, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Tmega16\+H\+VA, A\+Ttiny15, A\+Ttiny2313, A\+Ttiny48, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R2\+\_\+\+C\+O\+M\+P\+A\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E2A &Timer/\+Counter2 Compare Match A &A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R2\+\_\+\+C\+O\+M\+P\+B\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E2B &Timer/\+Counter2 Compare Match A &A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R2\+\_\+\+C\+O\+M\+P\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E2 &Timer/\+Counter2 Compare Match &A\+T90\+S4434, A\+T90\+S8535, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega163, A\+Tmega165, A\+Tmega165P, A\+Tmega169, A\+Tmega169P, A\+Tmega32, A\+Tmega323, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega8, A\+Tmega8535  \\\cline{1-4}
T\+I\+M\+E\+R2\+\_\+\+O\+V\+F\+\_\+vect &S\+I\+G\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W2 &Timer/\+Counter2 Overflow &A\+T90\+S4434, A\+T90\+S8535, A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega103, A\+Tmega128, A\+Tmega1284P, A\+Tmega16, A\+Tmega161, A\+Tmega162, A\+Tmega163, A\+Tmega165, A\+Tmega165P, A\+Tmega168P, A\+Tmega169, A\+Tmega169P, A\+Tmega32, A\+Tmega323, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega48P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega8, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R3\+\_\+\+C\+A\+P\+T\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+P\+U\+T\+\_\+\+C\+A\+P\+T\+U\+R\+E3 &Timer/\+Counter3 Capture Event &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega1284P, A\+Tmega162, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R3\+\_\+\+C\+O\+M\+P\+A\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E3A &Timer/\+Counter3 Compare Match A &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega1284P, A\+Tmega162, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R3\+\_\+\+C\+O\+M\+P\+B\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E3B &Timer/\+Counter3 Compare Match B &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega1284P, A\+Tmega162, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R3\+\_\+\+C\+O\+M\+P\+C\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E3C &Timer/\+Counter3 Compare Match C &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R3\+\_\+\+O\+V\+F\+\_\+vect &S\+I\+G\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W3 &Timer/\+Counter3 Overflow &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega1284P, A\+Tmega162, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+I\+M\+E\+R4\+\_\+\+C\+A\+P\+T\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+P\+U\+T\+\_\+\+C\+A\+P\+T\+U\+R\+E4 &Timer/\+Counter4 Capture Event &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
T\+I\+M\+E\+R4\+\_\+\+C\+O\+M\+P\+A\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E4A &Timer/\+Counter4 Compare Match A &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
T\+I\+M\+E\+R4\+\_\+\+C\+O\+M\+P\+B\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E4B &Timer/\+Counter4 Compare Match B &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
T\+I\+M\+E\+R4\+\_\+\+C\+O\+M\+P\+C\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E4C &Timer/\+Counter4 Compare Match C &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
T\+I\+M\+E\+R4\+\_\+\+O\+V\+F\+\_\+vect &S\+I\+G\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W4 &Timer/\+Counter4 Overflow &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
T\+I\+M\+E\+R5\+\_\+\+C\+A\+P\+T\+\_\+vect &S\+I\+G\+\_\+\+I\+N\+P\+U\+T\+\_\+\+C\+A\+P\+T\+U\+R\+E5 &Timer/\+Counter5 Capture Event &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
T\+I\+M\+E\+R5\+\_\+\+C\+O\+M\+P\+A\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E5A &Timer/\+Counter5 Compare Match A &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
T\+I\+M\+E\+R5\+\_\+\+C\+O\+M\+P\+B\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E5B &Timer/\+Counter5 Compare Match B &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
T\+I\+M\+E\+R5\+\_\+\+C\+O\+M\+P\+C\+\_\+vect &S\+I\+G\+\_\+\+O\+U\+T\+P\+U\+T\+\_\+\+C\+O\+M\+P\+A\+R\+E5C &Timer/\+Counter5 Compare Match C &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
T\+I\+M\+E\+R5\+\_\+\+O\+V\+F\+\_\+vect &S\+I\+G\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W5 &Timer/\+Counter5 Overflow &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
T\+W\+I\+\_\+vect &S\+I\+G\+\_\+2\+W\+I\+R\+E\+\_\+\+S\+E\+R\+I\+AL &2-\/wire Serial Interface &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega1284P, A\+Tmega16, A\+Tmega163, A\+Tmega168P, A\+Tmega32, A\+Tmega323, A\+Tmega328P, A\+Tmega32\+H\+VB, A\+Tmega406, A\+Tmega48P, A\+Tmega64, A\+Tmega8, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Ttiny48, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
T\+X\+D\+O\+N\+E\+\_\+vect &S\+I\+G\+\_\+\+T\+X\+D\+O\+NE &Transmission Done, Bit Timer Flag 2 Interrupt &A\+T86\+R\+F401  \\\cline{1-4}
T\+X\+E\+M\+P\+T\+Y\+\_\+vect &S\+I\+G\+\_\+\+T\+X\+BE &Transmit Buffer Empty, Bit Itmer Flag 0 Interrupt &A\+T86\+R\+F401  \\\cline{1-4}
U\+A\+R\+T0\+\_\+\+R\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T0\+\_\+\+R\+E\+CV &U\+A\+R\+T0, Rx Complete &A\+Tmega161  \\\cline{1-4}
U\+A\+R\+T0\+\_\+\+T\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T0\+\_\+\+T\+R\+A\+NS &U\+A\+R\+T0, Tx Complete &A\+Tmega161  \\\cline{1-4}
U\+A\+R\+T0\+\_\+\+U\+D\+R\+E\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T0\+\_\+\+D\+A\+TA &U\+A\+R\+T0 Data Register Empty &A\+Tmega161  \\\cline{1-4}
U\+A\+R\+T1\+\_\+\+R\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T1\+\_\+\+R\+E\+CV &U\+A\+R\+T1, Rx Complete &A\+Tmega161  \\\cline{1-4}
U\+A\+R\+T1\+\_\+\+T\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T1\+\_\+\+T\+R\+A\+NS &U\+A\+R\+T1, Tx Complete &A\+Tmega161  \\\cline{1-4}
U\+A\+R\+T1\+\_\+\+U\+D\+R\+E\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T1\+\_\+\+D\+A\+TA &U\+A\+R\+T1 Data Register Empty &A\+Tmega161  \\\cline{1-4}
U\+A\+R\+T\+\_\+\+R\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T\+\_\+\+R\+E\+CV &U\+A\+RT, Rx Complete &A\+T90\+S2313, A\+T90\+S2333, A\+T90\+S4414, A\+T90\+S4433, A\+T90\+S4434, A\+T90\+S8515, A\+T90\+S8535, A\+Tmega103, A\+Tmega163, A\+Tmega8515  \\\cline{1-4}
U\+A\+R\+T\+\_\+\+T\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T\+\_\+\+T\+R\+A\+NS &U\+A\+RT, Tx Complete &A\+T90\+S2313, A\+T90\+S2333, A\+T90\+S4414, A\+T90\+S4433, A\+T90\+S4434, A\+T90\+S8515, A\+T90\+S8535, A\+Tmega103, A\+Tmega163, A\+Tmega8515  \\\cline{1-4}
U\+A\+R\+T\+\_\+\+U\+D\+R\+E\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T\+\_\+\+D\+A\+TA &U\+A\+RT Data Register Empty &A\+T90\+S2313, A\+T90\+S2333, A\+T90\+S4414, A\+T90\+S4433, A\+T90\+S4434, A\+T90\+S8515, A\+T90\+S8535, A\+Tmega103, A\+Tmega163, A\+Tmega8515  \\\cline{1-4}
U\+S\+A\+R\+T0\+\_\+\+R\+X\+C\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T0\+\_\+\+R\+E\+CV &U\+S\+A\+R\+T0, Rx Complete &A\+Tmega162  \\\cline{1-4}
U\+S\+A\+R\+T0\+\_\+\+R\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T0\+\_\+\+R\+E\+CV &U\+S\+A\+R\+T0, Rx Complete &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega1284P, A\+Tmega165, A\+Tmega165P, A\+Tmega169, A\+Tmega169P, A\+Tmega325, A\+Tmega329, A\+Tmega64, A\+Tmega645, A\+Tmega649, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644  \\\cline{1-4}
U\+S\+A\+R\+T0\+\_\+\+T\+X\+C\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T0\+\_\+\+T\+R\+A\+NS &U\+S\+A\+R\+T0, Tx Complete &A\+Tmega162  \\\cline{1-4}
U\+S\+A\+R\+T0\+\_\+\+T\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T0\+\_\+\+T\+R\+A\+NS &U\+S\+A\+R\+T0, Tx Complete &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega1284P, A\+Tmega165, A\+Tmega165P, A\+Tmega169, A\+Tmega169P, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega64, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644  \\\cline{1-4}
U\+S\+A\+R\+T0\+\_\+\+U\+D\+R\+E\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T0\+\_\+\+D\+A\+TA &U\+S\+A\+R\+T0 Data Register Empty &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega1284P, A\+Tmega162, A\+Tmega165, A\+Tmega165P, A\+Tmega169, A\+Tmega169P, A\+Tmega325, A\+Tmega329, A\+Tmega64, A\+Tmega645, A\+Tmega649, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644  \\\cline{1-4}
U\+S\+A\+R\+T1\+\_\+\+R\+X\+C\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T1\+\_\+\+R\+E\+CV &U\+S\+A\+R\+T1, Rx Complete &A\+Tmega162  \\\cline{1-4}
U\+S\+A\+R\+T1\+\_\+\+R\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T1\+\_\+\+R\+E\+CV &U\+S\+A\+R\+T1, Rx Complete &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega1284P, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
U\+S\+A\+R\+T1\+\_\+\+T\+X\+C\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T1\+\_\+\+T\+R\+A\+NS &U\+S\+A\+R\+T1, Tx Complete &A\+Tmega162  \\\cline{1-4}
U\+S\+A\+R\+T1\+\_\+\+T\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T1\+\_\+\+T\+R\+A\+NS &U\+S\+A\+R\+T1, Tx Complete &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega1284P, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
U\+S\+A\+R\+T1\+\_\+\+U\+D\+R\+E\+\_\+vect &S\+I\+G\+\_\+\+U\+A\+R\+T1\+\_\+\+D\+A\+TA &U\+S\+A\+R\+T1, Data Register Empty &A\+T90\+C\+A\+N128, A\+T90\+C\+A\+N32, A\+T90\+C\+A\+N64, A\+Tmega128, A\+Tmega1284P, A\+Tmega162, A\+Tmega64, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
U\+S\+A\+R\+T2\+\_\+\+R\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T2\+\_\+\+R\+E\+CV &U\+S\+A\+R\+T2, Rx Complete &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
U\+S\+A\+R\+T2\+\_\+\+T\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T2\+\_\+\+T\+R\+A\+NS &U\+S\+A\+R\+T2, Tx Complete &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
U\+S\+A\+R\+T2\+\_\+\+U\+D\+R\+E\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T2\+\_\+\+D\+A\+TA &U\+S\+A\+R\+T2 Data register Empty &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
U\+S\+A\+R\+T3\+\_\+\+R\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T3\+\_\+\+R\+E\+CV &U\+S\+A\+R\+T3, Rx Complete &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
U\+S\+A\+R\+T3\+\_\+\+T\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T3\+\_\+\+T\+R\+A\+NS &U\+S\+A\+R\+T3, Tx Complete &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
U\+S\+A\+R\+T3\+\_\+\+U\+D\+R\+E\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T3\+\_\+\+D\+A\+TA &U\+S\+A\+R\+T3 Data register Empty &A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561  \\\cline{1-4}
U\+S\+A\+R\+T\+\_\+\+R\+X\+C\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T\+\_\+\+R\+E\+CV, S\+I\+G\+\_\+\+U\+A\+R\+T\+\_\+\+R\+E\+CV &U\+S\+A\+RT, Rx Complete &A\+Tmega16, A\+Tmega32, A\+Tmega323, A\+Tmega8  \\\cline{1-4}
U\+S\+A\+R\+T\+\_\+\+R\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T\+\_\+\+R\+E\+CV, S\+I\+G\+\_\+\+U\+A\+R\+T\+\_\+\+R\+E\+CV &U\+S\+A\+RT, Rx Complete &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+Tmega168P, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega3290, A\+Tmega3290P, A\+Tmega48P, A\+Tmega6450, A\+Tmega6490, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Ttiny2313  \\\cline{1-4}
U\+S\+A\+R\+T\+\_\+\+T\+X\+C\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T\+\_\+\+T\+R\+A\+NS, S\+I\+G\+\_\+\+U\+A\+R\+T\+\_\+\+T\+R\+A\+NS &U\+S\+A\+RT, Tx Complete &A\+Tmega16, A\+Tmega32, A\+Tmega323, A\+Tmega8  \\\cline{1-4}
U\+S\+A\+R\+T\+\_\+\+T\+X\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T\+\_\+\+T\+R\+A\+NS, S\+I\+G\+\_\+\+U\+A\+R\+T\+\_\+\+T\+R\+A\+NS &U\+S\+A\+RT, Tx Complete &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+Tmega168P, A\+Tmega328P, A\+Tmega48P, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Ttiny2313  \\\cline{1-4}
U\+S\+A\+R\+T\+\_\+\+U\+D\+R\+E\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+A\+R\+T\+\_\+\+D\+A\+TA, S\+I\+G\+\_\+\+U\+A\+R\+T\+\_\+\+D\+A\+TA &U\+S\+A\+RT Data Register Empty &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+Tmega16, A\+Tmega168P, A\+Tmega32, A\+Tmega323, A\+Tmega3250, A\+Tmega3250P, A\+Tmega328P, A\+Tmega3290, A\+Tmega3290P, A\+Tmega48P, A\+Tmega6450, A\+Tmega6490, A\+Tmega8, A\+Tmega8535, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Ttiny2313  \\\cline{1-4}
U\+S\+I\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+I\+\_\+\+O\+V\+E\+R\+F\+L\+OW &U\+SI Overflow &A\+Tmega165, A\+Tmega165P, A\+Tmega169, A\+Tmega169P, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Ttiny2313  \\\cline{1-4}
U\+S\+I\+\_\+\+O\+V\+F\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+I\+\_\+\+O\+V\+E\+R\+F\+L\+OW &U\+SI Overflow &A\+Ttiny26, A\+Ttiny43U, A\+Ttiny24, A\+Ttiny44, A\+Ttiny84, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861  \\\cline{1-4}
U\+S\+I\+\_\+\+S\+T\+A\+R\+T\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+I\+\_\+\+S\+T\+A\+RT &U\+SI Start Condition &A\+Tmega165, A\+Tmega165P, A\+Tmega169, A\+Tmega169P, A\+Tmega325, A\+Tmega3250, A\+Tmega3250P, A\+Tmega329, A\+Tmega3290, A\+Tmega3290P, A\+Tmega645, A\+Tmega6450, A\+Tmega649, A\+Tmega6490, A\+Ttiny2313, A\+Ttiny43U, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861  \\\cline{1-4}
U\+S\+I\+\_\+\+S\+T\+R\+T\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+I\+\_\+\+S\+T\+A\+RT &U\+SI Start &A\+Ttiny26  \\\cline{1-4}
U\+S\+I\+\_\+\+S\+T\+R\+\_\+vect &S\+I\+G\+\_\+\+U\+S\+I\+\_\+\+S\+T\+A\+RT &U\+SI S\+T\+A\+RT &A\+Ttiny24, A\+Ttiny44, A\+Ttiny84  \\\cline{1-4}
W\+A\+T\+C\+H\+D\+O\+G\+\_\+vect &S\+I\+G\+\_\+\+W\+A\+T\+C\+H\+D\+O\+G\+\_\+\+T\+I\+M\+E\+O\+UT &Watchdog Time-\/out &A\+Ttiny24, A\+Ttiny44, A\+Ttiny84  \\\cline{1-4}
W\+D\+T\+\_\+\+O\+V\+E\+R\+F\+L\+O\+W\+\_\+vect &S\+I\+G\+\_\+\+W\+A\+T\+C\+H\+D\+O\+G\+\_\+\+T\+I\+M\+E\+O\+UT, S\+I\+G\+\_\+\+W\+D\+T\+\_\+\+O\+V\+E\+R\+F\+L\+OW &Watchdog Timer Overflow &A\+Ttiny2313  \\\cline{1-4}
W\+D\+T\+\_\+vect &S\+I\+G\+\_\+\+W\+DT, S\+I\+G\+\_\+\+W\+A\+T\+C\+H\+D\+O\+G\+\_\+\+T\+I\+M\+E\+O\+UT &Watchdog Timeout Interrupt &A\+T90\+P\+W\+M3, A\+T90\+P\+W\+M2, A\+T90\+P\+W\+M1, A\+Tmega1284P, A\+Tmega168P, A\+Tmega328P, A\+Tmega32\+H\+VB, A\+Tmega406, A\+Tmega48P, A\+Tmega88P, A\+Tmega168, A\+Tmega48, A\+Tmega88, A\+Tmega640, A\+Tmega1280, A\+Tmega1281, A\+Tmega2560, A\+Tmega2561, A\+Tmega324P, A\+Tmega164P, A\+Tmega644P, A\+Tmega644, A\+Tmega16\+H\+VA, A\+Ttiny13, A\+Ttiny43U, A\+Ttiny48, A\+Ttiny45, A\+Ttiny25, A\+Ttiny85, A\+Ttiny261, A\+Ttiny461, A\+Ttiny861, A\+T90\+U\+S\+B162, A\+T90\+U\+S\+B82, A\+T90\+U\+S\+B1287, A\+T90\+U\+S\+B1286, A\+T90\+U\+S\+B647, A\+T90\+U\+S\+B646  \\\cline{1-4}
\end{longtabu}

\normalsize  

\doxysubsubsection{Macro Definition Documentation}
\mbox{\Hypertarget{group__avr__interrupts_ga1f6459a85cda682b2163a20af03ac744}\label{group__avr__interrupts_ga1f6459a85cda682b2163a20af03ac744}} 
\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}!BADISR\_vect@{BADISR\_vect}}
\index{BADISR\_vect@{BADISR\_vect}!$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxyparagraph{\texorpdfstring{BADISR\_vect}{BADISR\_vect}}
{\footnotesize\ttfamily \#define B\+A\+D\+I\+S\+R\+\_\+vect}


\begin{DoxyCode}{0}
\DoxyCodeLine{\textcolor{preprocessor}{\#include <\mbox{\hyperlink{interrupt_8h}{avr/interrupt.h}}>} }
\end{DoxyCode}


This is a vector which is aliased to \+\_\+\+\_\+vector\+\_\+default, the vector executed when an I\+SR fires with no accompanying I\+SR handler. This may be used along with the \mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{I\+S\+R()}} macro to create a catch-\/all for undefined but used I\+S\+Rs for debugging purposes. \mbox{\Hypertarget{group__avr__interrupts_ga68c330e94fe121eba993e5a5973c3162}\label{group__avr__interrupts_ga68c330e94fe121eba993e5a5973c3162}} 
\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}!cli@{cli}}
\index{cli@{cli}!$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxyparagraph{\texorpdfstring{cli}{cli}}
{\footnotesize\ttfamily \#define cli(\begin{DoxyParamCaption}{ }\end{DoxyParamCaption})}

Disables all interrupts by clearing the global interrupt mask. This function actually compiles into a single line of assembly, so there is no function call overhead. However, the macro also implies a {\itshape memory barrier} which can cause additional loss of optimization.

In order to implement atomic access to multi-\/byte objects, consider using the macros from $<$\mbox{\hyperlink{atomic_8h}{util/atomic.\+h}}$>$, rather than implementing them manually with \mbox{\hyperlink{group__avr__interrupts_ga68c330e94fe121eba993e5a5973c3162}{cli()}} and \mbox{\hyperlink{group__avr__interrupts_gaad5ebd34cb344c26ac87594f79b06b73}{sei()}}. \mbox{\Hypertarget{group__avr__interrupts_ga751c22101f7e8f2fbe792c64a81f8dba}\label{group__avr__interrupts_ga751c22101f7e8f2fbe792c64a81f8dba}} 
\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}!EMPTY\_INTERRUPT@{EMPTY\_INTERRUPT}}
\index{EMPTY\_INTERRUPT@{EMPTY\_INTERRUPT}!$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxyparagraph{\texorpdfstring{EMPTY\_INTERRUPT}{EMPTY\_INTERRUPT}}
{\footnotesize\ttfamily \#define E\+M\+P\+T\+Y\+\_\+\+I\+N\+T\+E\+R\+R\+U\+PT(\begin{DoxyParamCaption}\item[{}]{vector }\end{DoxyParamCaption})}

Defines an empty interrupt handler function. This will not generate any prolog or epilog code and will only return from the I\+SR. Do not define a function body as this will define it for you. Example\+: 
\begin{DoxyCode}{0}
\DoxyCodeLine{\mbox{\hyperlink{group__avr__interrupts_ga751c22101f7e8f2fbe792c64a81f8dba}{EMPTY\_INTERRUPT}}(ADC\_vect);}
\end{DoxyCode}
 \mbox{\Hypertarget{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}\label{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}} 
\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}!ISR@{ISR}}
\index{ISR@{ISR}!$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxyparagraph{\texorpdfstring{ISR}{ISR}}
{\footnotesize\ttfamily \#define I\+SR(\begin{DoxyParamCaption}\item[{}]{vector,  }\item[{}]{attributes }\end{DoxyParamCaption})}

Introduces an interrupt handler function (interrupt service routine) that runs with global interrupts initially disabled by default with no attributes specified.

The attributes are optional and alter the behaviour and resultant generated code of the interrupt routine. Multiple attributes may be used for a single function, with a space seperating each attribute.

Valid attributes are I\+S\+R\+\_\+\+B\+L\+O\+CK, I\+S\+R\+\_\+\+N\+O\+B\+L\+O\+CK, I\+S\+R\+\_\+\+N\+A\+K\+ED and \mbox{\hyperlink{group__avr__interrupts_gaa87c0c624b62f40a17539be6946c3e26}{I\+S\+R\+\_\+\+A\+L\+I\+A\+S\+O\+F(vect)}}.

{\ttfamily vector} must be one of the interrupt vector names that are valid for the particular M\+CU type. \mbox{\Hypertarget{group__avr__interrupts_gade46eb4e42cc9d56c19b1f91448f1b76}\label{group__avr__interrupts_gade46eb4e42cc9d56c19b1f91448f1b76}} 
\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}!ISR\_ALIAS@{ISR\_ALIAS}}
\index{ISR\_ALIAS@{ISR\_ALIAS}!$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxyparagraph{\texorpdfstring{ISR\_ALIAS}{ISR\_ALIAS}}
{\footnotesize\ttfamily \#define I\+S\+R\+\_\+\+A\+L\+I\+AS(\begin{DoxyParamCaption}\item[{}]{vector,  }\item[{}]{target\+\_\+vector }\end{DoxyParamCaption})}

Aliases a given vector to another one in the same manner as the I\+S\+R\+\_\+\+A\+L\+I\+A\+S\+OF attribute for the \mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{I\+S\+R()}} macro. Unlike the I\+S\+R\+\_\+\+A\+L\+I\+A\+S\+OF attribute macro however, this is compatible for all versions of G\+CC rather than just G\+CC version 4.\+2 onwards.

\begin{DoxyNote}{Note}
This macro creates a trampoline function for the aliased macro. This will result in a two cycle penalty for the aliased vector compared to the I\+SR the vector is aliased to, due to the J\+M\+P/\+R\+J\+MP opcode used.
\end{DoxyNote}
\begin{DoxyRefDesc}{Deprecated}
\item[\mbox{\hyperlink{deprecated__deprecated000002}{Deprecated}}]For new code, the use of \mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{I\+S\+R(..., I\+S\+R\+\_\+\+A\+L\+I\+A\+S\+O\+F(...))}} is recommended.\end{DoxyRefDesc}


Example\+: 
\begin{DoxyCode}{0}
\DoxyCodeLine{\mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{ISR}}(INT0\_vect)}
\DoxyCodeLine{\{}
\DoxyCodeLine{    PORTB = 42;}
\DoxyCodeLine{\}}
\DoxyCodeLine{}
\DoxyCodeLine{\mbox{\hyperlink{group__avr__interrupts_gade46eb4e42cc9d56c19b1f91448f1b76}{ISR\_ALIAS}}(INT1\_vect, INT0\_vect);}
\end{DoxyCode}
 \mbox{\Hypertarget{group__avr__interrupts_gaa87c0c624b62f40a17539be6946c3e26}\label{group__avr__interrupts_gaa87c0c624b62f40a17539be6946c3e26}} 
\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}!ISR\_ALIASOF@{ISR\_ALIASOF}}
\index{ISR\_ALIASOF@{ISR\_ALIASOF}!$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxyparagraph{\texorpdfstring{ISR\_ALIASOF}{ISR\_ALIASOF}}
{\footnotesize\ttfamily \#define I\+S\+R\+\_\+\+A\+L\+I\+A\+S\+OF(\begin{DoxyParamCaption}\item[{}]{target\+\_\+vector }\end{DoxyParamCaption})}

The I\+SR is linked to another I\+SR, specified by the vect parameter. This is compatible with G\+CC 4.\+2 and greater only.

Use this attribute in the attributes parameter of the I\+SR macro. \mbox{\Hypertarget{group__avr__interrupts_ga5fc50a0507a58e16aca4c70345ddac6a}\label{group__avr__interrupts_ga5fc50a0507a58e16aca4c70345ddac6a}} 
\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}!ISR\_BLOCK@{ISR\_BLOCK}}
\index{ISR\_BLOCK@{ISR\_BLOCK}!$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxyparagraph{\texorpdfstring{ISR\_BLOCK}{ISR\_BLOCK}}
{\footnotesize\ttfamily \#define I\+S\+R\+\_\+\+B\+L\+O\+CK}

Identical to an I\+SR with no attributes specified. Global interrupts are initially disabled by the A\+VR hardware when entering the I\+SR, without the compiler modifying this state.

Use this attribute in the attributes parameter of the I\+SR macro. \mbox{\Hypertarget{group__avr__interrupts_ga8b4c7e44627db0a60d676213add42d64}\label{group__avr__interrupts_ga8b4c7e44627db0a60d676213add42d64}} 
\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}!ISR\_NAKED@{ISR\_NAKED}}
\index{ISR\_NAKED@{ISR\_NAKED}!$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxyparagraph{\texorpdfstring{ISR\_NAKED}{ISR\_NAKED}}
{\footnotesize\ttfamily \#define I\+S\+R\+\_\+\+N\+A\+K\+ED}

I\+SR is created with no prologue or epilogue code. The user code is responsible for preservation of the machine state including the S\+R\+EG register, as well as placing a \mbox{\hyperlink{group__avr__interrupts_ga3b991e8168db8fc866e31f9a6d10533b}{reti()}} at the end of the interrupt routine.

Use this attribute in the attributes parameter of the I\+SR macro. \mbox{\Hypertarget{group__avr__interrupts_ga44569cb914d2aaf8fbb436f8f7c4ca68}\label{group__avr__interrupts_ga44569cb914d2aaf8fbb436f8f7c4ca68}} 
\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}!ISR\_NOBLOCK@{ISR\_NOBLOCK}}
\index{ISR\_NOBLOCK@{ISR\_NOBLOCK}!$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxyparagraph{\texorpdfstring{ISR\_NOBLOCK}{ISR\_NOBLOCK}}
{\footnotesize\ttfamily \#define I\+S\+R\+\_\+\+N\+O\+B\+L\+O\+CK}

I\+SR runs with global interrupts initially enabled. The interrupt enable flag is activated by the compiler as early as possible within the I\+SR to ensure minimal processing delay for nested interrupts.

This may be used to create nested I\+S\+Rs, however care should be taken to avoid stack overflows, or to avoid infinitely entering the I\+SR for those cases where the A\+VR hardware does not clear the respective interrupt flag before entering the I\+SR.

Use this attribute in the attributes parameter of the I\+SR macro. \mbox{\Hypertarget{group__avr__interrupts_ga3b991e8168db8fc866e31f9a6d10533b}\label{group__avr__interrupts_ga3b991e8168db8fc866e31f9a6d10533b}} 
\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}!reti@{reti}}
\index{reti@{reti}!$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxyparagraph{\texorpdfstring{reti}{reti}}
{\footnotesize\ttfamily \#define reti(\begin{DoxyParamCaption}{ }\end{DoxyParamCaption})}

Returns from an interrupt routine, enabling global interrupts. This should be the last command executed before leaving an I\+SR defined with the I\+S\+R\+\_\+\+N\+A\+K\+ED attribute.

This macro actually compiles into a single line of assembly, so there is no function call overhead. \mbox{\Hypertarget{group__avr__interrupts_gaad5ebd34cb344c26ac87594f79b06b73}\label{group__avr__interrupts_gaad5ebd34cb344c26ac87594f79b06b73}} 
\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}!sei@{sei}}
\index{sei@{sei}!$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxyparagraph{\texorpdfstring{sei}{sei}}
{\footnotesize\ttfamily \#define sei(\begin{DoxyParamCaption}{ }\end{DoxyParamCaption})}

Enables interrupts by setting the global interrupt mask. This function actually compiles into a single line of assembly, so there is no function call overhead. However, the macro also implies a {\itshape memory barrier} which can cause additional loss of optimization.

In order to implement atomic access to multi-\/byte objects, consider using the macros from $<$\mbox{\hyperlink{atomic_8h}{util/atomic.\+h}}$>$, rather than implementing them manually with \mbox{\hyperlink{group__avr__interrupts_ga68c330e94fe121eba993e5a5973c3162}{cli()}} and \mbox{\hyperlink{group__avr__interrupts_gaad5ebd34cb344c26ac87594f79b06b73}{sei()}}. \mbox{\Hypertarget{group__avr__interrupts_ga67cd0dea412157775c2f2a3ffe9fb8ff}\label{group__avr__interrupts_ga67cd0dea412157775c2f2a3ffe9fb8ff}} 
\index{$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}!SIGNAL@{SIGNAL}}
\index{SIGNAL@{SIGNAL}!$<$avr/interrupt.h$>$: Interrupts@{$<$avr/interrupt.h$>$: Interrupts}}
\doxyparagraph{\texorpdfstring{SIGNAL}{SIGNAL}}
{\footnotesize\ttfamily \#define S\+I\+G\+N\+AL(\begin{DoxyParamCaption}\item[{}]{vector }\end{DoxyParamCaption})}

Introduces an interrupt handler function that runs with global interrupts initially disabled.

This is the same as the I\+SR macro without optional attributes. \begin{DoxyRefDesc}{Deprecated}
\item[\mbox{\hyperlink{deprecated__deprecated000001}{Deprecated}}]Do not use \mbox{\hyperlink{group__avr__interrupts_ga67cd0dea412157775c2f2a3ffe9fb8ff}{S\+I\+G\+N\+A\+L()}} in new code. Use \mbox{\hyperlink{group__avr__interrupts_gad28590624d422cdf30d626e0a506255f}{I\+S\+R()}} instead. \end{DoxyRefDesc}
