; ModuleID = 'probe7.5ce240b3b4b63625-cgu.0'
source_filename = "probe7.5ce240b3b4b63625-cgu.0"
target datalayout = "E-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128-Fn32"
target triple = "aarch64_be-unknown-netbsd"

; core::f64::<impl f64>::copysign
; Function Attrs: inlinehint uwtable
define internal double @"_ZN4core3f6421_$LT$impl$u20$f64$GT$8copysign17hf282c5af3beb9954E"(double %self, double %sign) unnamed_addr #0 {
start:
  %0 = alloca [8 x i8], align 8
  %1 = call double @llvm.copysign.f64(double %self, double %sign)
  store double %1, ptr %0, align 8
  %_0 = load double, ptr %0, align 8
  ret double %_0
}

; probe7::probe
; Function Attrs: uwtable
define void @_ZN6probe75probe17h9974609e01c4d678E() unnamed_addr #1 {
start:
; call core::f64::<impl f64>::copysign
  %_1 = call double @"_ZN4core3f6421_$LT$impl$u20$f64$GT$8copysign17hf282c5af3beb9954E"(double 1.000000e+00, double -1.000000e+00)
  ret void
}

; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
declare double @llvm.copysign.f64(double, double) #2

attributes #0 = { inlinehint uwtable "probe-stack"="inline-asm" "target-cpu"="generic" }
attributes #1 = { uwtable "probe-stack"="inline-asm" "target-cpu"="generic" }
attributes #2 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }

!llvm.module.flags = !{!0}
!llvm.ident = !{!1}

!0 = !{i32 8, !"PIC Level", i32 2}
!1 = !{!"rustc version 1.86.0 (05f9846f8 2025-03-31) (built from a source tarball)"}
